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To: Scrapps who wrote (15613)	2/15/1999 8:19:00 PM
From: MileHigh	Respond to of 93625

ISSCC: Toshiba boasts FRAM prototype with DRAM-like speeds By Anthony Cataldo EE Times (02/15/99, 10:14 a.m. EDT) KAWASAKI, Japan — Toshiba Corp. may be poised to realize a production-worthy ferroelectric RAM-a technology long pursued by Japanese semiconductor companies as the ultimate non-volatile memory. In a paper to be presented in San Francisco this week at the International Solid-State Circuits Conference, Toshiba researchers will describe a 16-kbit FRAM prototype that they say achieves DRAM-like speeds for both initial and random access. The researchers attribute the performance leap to a revamped cell-plate line drive technique. The ISSCC paper builds on a previous Toshiba proposal to halve the conventional FRAM cell size by chaining together capacitor and transistor pairs eight at a time. That scheme allows each FRAM cell to be placed at every intersection of the word and bit line, said Daisaburo Takashima, research scientist for Toshiba's Advanced Semiconductor Devices Research Laboratories. Toshiba previously employed a half-Vdd cell-plate scheme without refresh to increase operational speed. But that scheme required a high minimum Vdd because of the low voltage applied to the ferroelectric capacitor. So Toshiba researchers revamped the cell-plate line drive technique to lower the voltage while preserving the speed advantage. As in the previous design, the one-transistor/one-capacitor FRAM cells are arranged in a group of eight to form a block, along with a special block-selecting transistor for each. To obtain random access, all the transistors are turned on, and the capacitors are short-circuited during standby to keep the word lines high and hold the cell data steady (in a conventional approach the capacitors are turned off; hence the cell data floats). During the active cycle, the word line is pulled down, the selected transistor turned off and the block-selecting signal turned on. Then the plate line is pulled up to apply the Vdd bias so that the bit line is terminated at the selected capacitor. "Random access is realized through short-circuited capacitors so we can get high random access and packing density," Takashima said. Toshiba's plate-line drive scheme uses existing resources and meshes with its block-selecting method. No extra metal is needed to drive the heavy capacitive load of the plate line; rather, the first metal layer is used both as an interconnect between the transistor and the capacitor and the plate line. That lets Toshiba reduce resistance to 1/25 by taking advantage of the existing aluminum wiring, instead of requiring the platinum electrodes common in many FRAM architectures. The plate line connects with two cell blocks for a total of 16 FRAM cells, reducing the plate driver area by 80 percent and increasing drivability by 3.2 times, the researchers said. Yet the resulting rise in plate capacitance is kept below 20 percent, since only the selected cell contributes to parasitic capacitance (the others stay short-circuited). Total plate-line drive time is cut to 7 ns from the 30 to 100 ns of the conventional approach, Takashima said. All told, the prototype chip offers a 37-ns access time and an 80-ns read/write cycle time at 3.3 V.