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To: FJB who wrote (31144)	2/22/1999 11:32:00 AM
From: Jim McMannis	Read Replies (1) \| Respond to of 33344

Robert, I couldn't find the release. If you turn on CNBC now you see the blurb. Are you still brown nosing Paul Engel? Jim

To: FJB who wrote (31144)	2/22/1999 12:32:00 PM
From: Pravin Kamdar	Respond to of 33344

CNBC really messed up that report. I'm starting to see Rene San Miguel's true knowledge of the industry. He also said that Intel started the trend by adding cache to the Celeron processor, and that AMD has followed the trend, to a lesser degree, with their new K6-3! Holly cow. Basically, IBM has just announced a process capable of good logic and memory performance (while not being optimized for either), and with good density. This process should enable the design of many integrated devices... such as PCOAC. Pravin.

To: FJB who wrote (31144)	2/22/1999 8:32:00 PM
From: Joe NYC	Respond to of 33344

Bob, You are right, IBM's press release doesn't amount to anything immediate, but eventually, the processor and memory will end up on one chip. Ideally, you would need some flash memory as main memory, fast SRAM for L2, hopefully large enough so that the whole application of the information appliance fits in, and the rest of the PCOAC. This thing would eliminate the latencies of DRAM and hard disk, and could perform well under fairly low clock speeds, run cool and not use too much power. Joe