ibm...and dram
IBM embeds DRAM in 0.18-micron ASICs
By David Lammers
EE Times
(02/22/99, 6:00 p.m. EDT)
EAST FISHKILL, N.Y. — Though embedded DRAM has gotten off to a slow start in the market, IBM Corp. has customers lining up for its new SA-27E logic process that will accept DRAM macros with as few as five or less mask penalties.
According to Subu Iyer, embedded DRAM manager at IBM's microelectronics division, customers waiting to use IBM's new process include one major hard-disk-drive manufacturer. IBM will issue a design kit for SA-27E in April, and will begin making parts in the 0.18-micron process late this year. For most customers, embedded DRAM will add about 25 percent to the cost of a part compared to one produced with the straight logic process.
The embedded DRAM technology is based on what IBM calls its "value" 0.18-micron process, with six layers of copper interconnect, a poly gate dimension of 0.15 micron and an Leff of 0.11 micron at the nFET. The process yields a gate delay of 33 picoseconds.
When IBM first described its embedded DRAM technology at the International Electron Devices Meeting last December, the cell size for a bit of embedded DRAM was said to be 0.62 microns2. By tightening up the back-end wiring, that has since been shrunk to 0.56 microns2, or roughly 1.5 times larger than the cell size in IBM's standalone 64-Mbit DRAM technology.
Embedded DRAM most often competes against SRAM; IBM's six-transistor SRAM cell, at the same process technology, measures 4.8 microns2 — about eight times larger than the embedded DRAM cell size. But the SRAM is made with a straight logic process and requires no additional mask layers to construct, so any die-size savings found by using embedded DRAM must be balanced against the 25 percent higher process cost required to create the trench capacitor for the embedded DRAM.
Iyer said some customers will consider embedded DRAM at the 2-Mbit density point, where embedded DRAM will take 4.6 millimeters2 and the same 2-Mbits of SRAM will consume roughly 35-to-40 mm2. At 4-Mbits and higher, the benefits of using embedded DRAM "are absolutely clear," Iyer said.
While some customers will stick with SRAM for raw performance, embedded DRAM is far from slow in the SA-27E process. According to the spec sheet, the worst-case access time is 13 ns for a first access, and 9 ns nominally. In many cases, the second access will occur in just 5 ns. The page access time is rated at 6.6 ns.
Many design engineers recoiled from embedded DRAM last year when they realized that logic circuits would take a significant performance hit when produced in a process that accommodated embedded DRAM, Iyer said. And hard-disk-drive makers grew wary of embedded DRAM last year as more than one design introduced with 4-Mbits of on-board DRAM proved to be obsolete at introduction, when 16-Mbits turned out to be the optimum density. Several digital still camera makers also resisted eDRAM for cost reasons.
Hard-drive controllers intended for the Firewire storage subsystems require at least 100-MHz performance, and "no person on the block could deliver that," Iyer said.
While said some drive companies want to add embedded DRAM to their controllers, according to another source, others will combine the analog read-control function with digital control logic and keep the DRAM as a discrete device.
The attraction of embedded DRAM is on-chip bandwidth, or as IBM vice president Bijan Divari put it, keeping the logic and data inside the same house rather than having to go next door to another chip to fetch data.
Rather than use a compiler approach, IBM's DRAM macros can be built in 1-Mbit increments. The memory blocks are libraries that appear to a designer just like any other ASIC core. Sixteen 1-Mbit blocks create one macro, which links to a design's logic blocks via a 256-bit bus. A second macro would add a second 256-bit bus, adding up to a typical 64-Mbit macro with a 1,024-bit-wide highway to the logic.
Iyer said that as much as 50 gigabytes/second of bandwidth is possible at the 200-MHz bus frequency. The amount of memory is limited by the die size. A centimeter on a side is considered typical in the ASIC world, but some designs will use the full field size of 18 mm on a side, and some customers will stitch a 22 mm2 die to get the maximum amount — 24 million gates — of density. A 16-Mbit macro requires 20.8 mm2.
Some customers are considering putting an ARM or PowerPC core on a die, adding SRAM as L1 and L2 cache, and embedded DRAM as an L3 cache. "Each customer we are talking with has a different approach," Iyer said. "The important thing to note is that this is just part of our ASIC methodology. DRAM appears to the designer as just another core, and we are completely flexible."
Iyer said IBM engineers worked hard on an on-chip built-in self-test (BIST) engine that tests the macro "in every pattern known to man." The BIST cell also means that the entire die can be tested with a logic tester, rather than requiring separate memory and logic test passes.
Howard Kalter, an IBM Fellow who worked on IBM's embedded DRAM technology until his recent retirement, said that if an application requires 2.5-V or 2.3-V peripheral analog circuits, the same thick oxide layer needed for the analog circuitry can be used in the creation of the memory arrays. In those cases, only two or three additional mask layers will be needed, which would keep the cost differential somewhat lower.
Kalter said the development group working on IBM's embedded DRAM technology will require about three months for reliability testing, both voltage and thermal testing. After that, some tweaking of the process will undoubtably be required, meaning that it may be October or later before chips can begin to be manufactured at the company's facilities in Burlington, Vt.
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