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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Petz who wrote (51023)	2/26/1999 10:05:00 AM
From: Scumbria	Respond to of 1572099

Petz, There is probably some pathological program code out there that exercises the L2 cache and the FPU on almost every cycle. An FFT on a very large data set should do it. This is an interesting point, but it is hard for me to imagine any real code which misses the L1, and hits in the L2 on almost every cycle. The reasons for this are: 1. The first miss of each L1 cache line causes a linefill, and the rest of the line is serviced by the L1. 2. Code that causes a lot of L1 misses (like Linpac) also cause a lot of L2 misses. 3. Even if such code existed- the longer latencies to the L2 would cause the processor to slow to 1/2 or 1/3 speed, resulting in lower power consumption. Scumbria