mindmeld - Thank you for that information. I discovered another post on terabit routers which I copied from the MRVC thread. My thanks to signist who posted it there.
Will 1999 be the year of the terabit router?
February 15, 1999, Issue: 1147
Section: Inside: Network Equipment
Revving Up For Terabit Speeds -- Internet growth lays basis
for new router market.
John H. Mayer
Will 1999 be the year of the terabit router? That's the question a bevy of start-ups are posing as they rush to market new ultra-high-end switch routers capable of terabit speeds.
Proposing ground-breaking architectures, new venture-backed companies such as Argon Networks, Avici Systems, Juniper Networks, NEO Networks, Nexabit Networks, Netcore Systems, Pluris, and Torrent Networking Technologies are betting that escalating use of the Internet, spurred by the introduction of faster access technologies and new applications like e-commerce and voice-over-Internet protocol, will build a convincing case for a new generation of highly scalable routers.
The numbers seem to back them up.
"Traffic is growing so rapidly it's bizarre," said analyst John Ryan of Ryan, Hankin and Kent Inc., South San Francisco. Ryan's firm has opted to use a relatively "conservative" annual growth estimate for its demand-modeling service of 700%.
"What that means is, if you put into your network a new-generation router and it's only 10% utilized today, by the end of the year it will be 70% utilized and nearing exhaustion," he said. "Within the year, you have to replace it and that
makes it extremely difficult to manage and plan the network rather than just respond to fires."
Avici Systems Inc. and its competitors hope to help their customers stretch out the life of their network investments. Avici is building an all-optical packet switch/router based on a Direct Connect Fabric that mounts a 60-Gbit/s router on each line card. The rack-mountable Terabit Switch Router (TSR) houses up to 20 line cards, allowing ISPs to extend capacity as needed.
In its first derivation, the TSR will feature line cards with four OC-12 (622-Mbit/s) SONET and a single OC-48 (2.4-Gbit/s) link that will support 200,000 routes. Within a year, the system will also support faster OC-192 (10-Gbit/s) SONET capability, according to Pete Chadwick, marketing director at Avici, North Billerica, Mass.
The TSR is in trials at three of Avici's customers, and production versions are scheduled for midyear.
Flexibility is also a key selling point for these new network-equipment vendors.
"The challenge for ISPs right now is to navigate the transition from OC-3 [155-Mbit/s] and OC-12-based cores to OC-48," said Joe Furgerson, vice president of marketing at Juniper Networks Inc., Mountain View, Calif.
"The way they architect their POPs, they've got to translate bandwidth in the core to bandwidth at the access layer, and that's something that's undergoing its own period of change," he said. "Whereas the internal architecture at these POPs was previously predicated on technologies such as FDDI and ATM OC-3, as the network goes to higher speeds they're starting to migrate to Gigabit Ethernet or ATM OC-12."
One of the few router vendors to have actually brought its product to market, Juniper's M40 Internet backbone router features a 40-Gbit/s switching fabric and supports OC-3, OC-12, OC-48, and DS2 interfaces. Much of Juniper's design effort went into JUNOS, an Internet-optimized route operating system.
"There's no doubt that bandwidth is critical, but scaling is as much a dimension of software as it is of hardware," Furgerson noted.
Adding value
One key value-add these new router vendors are focusing on is improved traffic-engineering capabilities. "That's something that routers don't do really well right now, and the consequence is, router resources are often chronically under-utilized," Ryan said.
Terabit-router vendors are attempting to meet that need by supporting MultiProtocol Label Switching, the emerging IETF standard that allows traffic to be marked for security and quality-of-service (QoS) parameters, and other approaches. Avici's TSR, for example, will guarantee multiple QoS tiers of prioritized network capacity.
Like most of the announced terabit routers, which rely heavily on ASIC design expertise, Avici's TSR is implemented in seven custom-designed ASICs. Each implements a specific function such as address lookup at Layer 3 or multicast expansion.
Juniper's M40 provides extensive traffic-engineering, multicast, and class-of-service capabilities through a Packet Forwarding Engine that is implemented in four ASICs manufactured by IBM Microelectronics. Three of the ASICs are large, million-plus-gate devices, according to Furgerson.
"These weren't trivial chips," he noted. "What IBM offered was a superior 0.25-micron process for communications, as well as a greater capacity to handle packaging with a large number of I/O."
The Cisco factor
If fledgling network-equipment suppliers expect to win market share, they'll have to steal it from Cisco Systems Inc., according to analysts. The San Jose-based network-equipment giant owns well over 70% of the Internet-router market.
Cisco's high-end offerings-the 12000 series Gigabit Switch Routers (GSR)-which handle OC-12 levels of traffic and will scale to OC-48-have been well received. But until Cisco scales its products up the performance ladder, it's open to competition at the high end.
"Relative to Cisco, we've got wire-rate performance, regardless of packet size, and more configuration flexibility," Juniper's Furgerson said.
Although no one expects Cisco to lose its lead, there's ample opportunity for a well-placed, well-managed start-up to garner a substantial share of a market growing so fast that even established vendors can't keep up, Ryan said.
Ryan, Hankin, and Kent estimate that the North American market for multigigabit routers will jump from $500 million in 1999 to more than $2 billion in 2001. A second factor is a fairly large exodus of technical experts from Cisco, many of whom have taken their skills to this latest group of start-ups.
"Given that, it isn't unreasonable for some of these companies to be taken seriously," Ryan said.
To improve their chances of success, some terabit-router start-ups are partnering with large network-equipment suppliers. Avici, for example, has sold a 20% stake to Northern Telecom Ltd., while Juniper Networks has accepted a $10 million investment from Lucent Technologies Inc.
"For them to succeed in the very long run, it makes more sense for them to ally with bigger companies with more established finance channels and broader product lines," Ryan said.
Off-the-shelf options
With demand for bandwidth growing so rapidly, getting a product to market as fast as possible is crucial for these new router vendors. A variety of new off-the-shelf OC-48 circuits are helping accelerate the design pace.
In its new M40 router, for instance, Juniper opted to use customized versions of half-a-dozen telecom and datacom ICs from Applied Micro Circuits Corp., San Diego.
"Time-to-market is everything for a start-up, and when they came to us, they had an extremely aggressive development schedule," said Ken Prentiss, AMCC's telecommunications product manager.
Among those devices were the S3041 and S3042, an 8-bit transmitter and receiver chipset used to multiplex and demultiplex slower-speed circuits up to the OC-48 level, and the S3048, an OC-48 clock recovery unit.
"The overall market driver is the opening up of WDM [Wave Division Multiplexing] circuits in the backbone, which means you have much more stringent concerns about jitter and latency," Juniper's' Furgerson said. "One of our greatest challenges was bringing an OC-48 solution to market that could meet those fairly stringent jitter and latency standards, and AMCC helped us meet that goal."
Over the past few months, IC suppliers have brought to market a number of 2.5- Gbit/s PHY devices that promise to help designers cut cost and lower power consumption through higher levels of integration. Vitesse Semiconductor Corp., Camarillo, Calif., a leading supplier of high-speed gallium arsenide
circuits, recently announced the VSC8120 and VSC8121.
The VSC8120 is a clock and data recovery unit that allows designers to adjust
the sampling point within the data eye to optimize bit error rate. The IC uses a
selectable input reference clock of either 19, 39, 78, or 155 MHz, and maintains
the clock output in the absence of data. It also exceeds the jitter tolerance,
transfer, and generation performance required to meet SONET/SDH standards.
To provide a high-speed system clock in 2.5-Gbit/s systems, Vitesse offers the
VSC8121 2.5-Gbit/s clock multiplication unit. The monolithic device features an
on-chip loop filter and configurable reference clock, which is selectable for 51,
78, or 155 MHz. The 3.3-V part has a maximum power dissipation rating of 700
mW.
"Designers used to have to purchase very expensive crystals to achieve this
level of performance," said Gregg Borodaty, Vitesse's director of marketing for
telecom products. "Now they can use a much lower crystal, like a 77-MHz, for
example, that has extremely good performance, and then with our clock
multiplier generate a 2.5-Gbit/s clock with very low phase noise."
Bipolar alternatives
While data rates of 2.5 Gbits/s and higher were once considered the sole
domain of gallium arsenide, new bipolar offerings are claiming comparable
performance at lower power. "A couple of years ago, there was a perception
that only GaAs could be used for 2.5 Gbits/s and above," AMCC's Prentiss said.
"That's absolutely not true."
In its new line, AMCC includes the S3047, a SONET/SDH/ATM OC-48
2.5-Gbit/s clock and data recovery IC that uses a self-acquisition
phase-locked-loop (PLL) to eliminate the need for an external clock. The chip
offers a lower-cost solution that saves designers of optical modules and Dense
Wave Division Multiplexing applications substantial real estate and cost.
"Most PLLs use some kind of external source as a reference and then multiply
up," Prentiss said. "The S3047 can acquire lock-to-data without the need for that
lower-speed reference, so you don't have to buy an external crystal oscillator,
which, depending on what type you use, can cost you anywhere from $20 to $50
and dissipate half a watt of power."
The company claims that the device-priced at $145 in 100s and packaged in a
32-pin LLCC that measures just 7 mm square-is one-third the cost and half the
size of other solutions.
How far AMCC can take bipolar technology remains to be seen. But, thanks to
a partnership with IBM, AMCC plans to implement a new silicon-germanium
process in its next fab, which company officials claim will scale to 40 GHz.
A number of new ICs are targeted at increasing line-card densities. Last year,
PMC-Sierra Inc., Vancouver, British Columbia, announced a
Packet-over-SONET/SDH (POS-PHY) Level 2 PHY specification designed to
optimize bandwidth utilization by enabling next-generation routers to connect
directly to SONET/SDH rings without requiring an intermediate layer. Endorsed
by the Saturn POS-PHY Subworking group, a collection of packet and
ATM-equipment manufacturers, the interface is a subset of the Utopia Level 2
specification and allows up to 800-Mbit/s throughput.
PMC-Sierra also introduced the first PHY device to meet the S/UNI-TETRA
specification. The 3.3-V dual-mode ATM cell processor and POS frame
processor help enable high-density OC-3 port card designs by integrating four
OC-3c channels into a single chip.
With a new line of fiber-optic transceivers from Hewlett-Packard Co. called
MT-RJ, designers can redefine traditional line-card port-density limitations,
according to Tim Pezzaro, PMC-Sierra's ATM/SONET/SDH marketing
manager. "Together, the two technologies allow you to build a 16-port OC-3 line
card for a standard chassis," he noted.
The S/UNI-TETRA also connects directly to PMC-Sierra's PM7322
RCMP-800 ATM Layer cell processor and PM73487 QRT/PM73488 QSE
switching chipset over an industry-standard Utopia Level II-compliant bus for
ATM-based applications. In a SBGA package, the chip is $249 in 1,000s.
In December, PMC-Sierra added an extension to its POS-PHY Level 2
interface with a new Level 3 specification that supports throughput up to 3.2
Gbits/s.
At the same time, the company introduced the first PHY device to support the
new specification. The PM5357 S/UNI-622-POS is a 3.3-V dual-mode PSO
frame processor and ATM cell processor capable of operating at 155 or 622
Mbits/s (OC-3 and OC-12 speeds, respectively). It integrates a
serializer-deserializer, clock recovery, and clock synthesis functions with a
frame and cell processor. The PM 5357 S/UNI-622-POS sells for $249 in
1,000s in an SBGA.
Onward to OC-192
In the meantime, with demand for bandwidth seemingly without a ceiling, IC
vendors are beginning to work on building out their product lines for
next-generation OC-192 applications.
"We've seen WDM delay the emergence of OC-192," Vitesse's Borodaty said.
"But now that many manufacturers are starting to realize you can take 40
2.5-Gbit/s signals and put them on one fiber, they're saying why not take
OC-192 and put it on one fiber as well; so there's been quite a bit of activity in
the market."
While Vitesse already offers a multiplexer and demultiplexer for OC-192
applications, the company plans to bring out a wealth of products this year. "I
think the market will really start to take off here over the next year or so,"
Borodaty predicted.
-John H. Mayer is a freelance writer based in Belmont, Mass.
Copyright ® 1999 CMP Media Inc.
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