SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?


To: Paul Engel who wrote (75461)3/5/1999 2:18:00 AM
From: greenspirit  Read Replies (1) | Respond to of 186894
 
Paul, a news item only you could love, or understand :-) Enjoy!

DSAD process for deposition of inter layer dielectric (Assignee -- Intel Corporation)

March 5, 1999

U.S. Patents via NewsEdge Corporation : Abstract: A method of depositing an inter layer dielectric. A first layer using plasma enhanced chemical vapor deposition (CVD) is deposited. It is followed by a second layer, deposited using sub atmospheric CVD. The second layer is argon sputter etched.

Ex Claim Text: A method of forming an inter layer dielectric to isolate a plurality of structures with a height, a top and a bottom, formed on a substrate, and having edges forming corners between said structures, the method comprising the steps of: forming a seed layer between said structures by plasma enhanced chemical vapor deposition of a TEOS based oxide that substantially maintains the edges of the structures on the substrate; forming a gapfill layer by sub atmospheric chemical vapor deposition of the TEOS based oxide that substantially maintains the edges of the structures on the substrate; and after forming the gapfill layer, sputter etching said gapfill layer formed by the sub atmospheric chemical vapor deposition by argon sputter etching, wherein a part of a material removed from the gapfill layer by the sputter etching is deposited in the corners, wherein a tensile stress of the gapfill layer balances the compressive stress of the seed layer and the third dielectric layer, thereby producing an overall compressive stress between 0.5e9 and 1.5e9 dyne per square centimeter as result of the layers.

Patent Number: 5872064

Issue Date: 1999 02 16

If you would like to purchase a copy of this patent, please call MicroPatent at 800-648-6787.





To: Paul Engel who wrote (75461)3/5/1999 10:32:00 AM
From: Sonny McWilliams  Read Replies (1) | Respond to of 186894
 
Paul. I just wanted to make sure that those "outside guests" had something to go by. gg.

Yes, Joe Kernan is into all this stuff, now that he has a cpt. Once you get one, you are bitten by the bug.

BTW, he is keeping track of all those gurus who have called for a 5 to 10% correction in the market.

Thanks again for all your contributions.

Sonny