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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?


To: kash johal who wrote (51768)3/6/1999 8:46:00 PM
From: Ali Chen  Respond to of 1572637
 
Kash, thanks for correcting my terminology. It sometimes
hard to perform correct translation between languages,
and I am not a chip designer.

<K7 will be demonstrated in a few weeks>
It would be nice if some idiot could eventually
ask a straight question at what core
voltage it runs:)
You know, we are having a dispute here,
is it 2.5V as for K6, or about one volt less as
Maxwell reported sometime ago :)

Take care,

- Ali



To: kash johal who wrote (51768)3/6/1999 10:50:00 PM
From: Elmer  Read Replies (1) | Respond to of 1572637
 
Re: "Re <Sorry Ali but you got things backwards. 'Sequential gates'? You mean combinational gates between sequential elements.>

Just to jump in here. You were correct except for the terminology.

There are always a "series" of logic gates ( Combinatorial function) required to perform a certain function. Designers split up this series by inserting a "clocked" element (a flip-flop - also known as a "sequential" element."

I believe you were actually intending to agree with me as the above quote was mine, not Ali's. I was correcting Ali's misunderstanding of basic design principles. I might add though that a latch is a sequential element as well as a Flip-Flop.

EP



To: kash johal who wrote (51768)3/7/1999 1:42:00 AM
From: Tenchusatsu  Read Replies (1) | Respond to of 1572637
 
<The K7 is even more pipelined than the PII family and should give an even faster clcok rate than the PII in the same process.>

Even more pipelined? Last time I checked, the K7 has about as many pipeline stages as the P6 core. If the K7 is going to achieve a faster clock rate than the P6, it'll be due to a shorter critical path in each pipeline stage.

Tenchusatsu