Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Elmer who wrote (51772)	3/6/1999 11:08:00 PM
From: grok	Respond to of 1573211

I don't know what Gopher's source is but I think I remember the Intel released some diagram that shows an x86 core in the corner. I don't think that the diagram has to be taken literally. It seems more likely that Merced has a preprocessor that converts x86 instructions into IA64 native instructions in the same way that P6 converts x86 into ROPs or whatever Intel calls the RISC-like operations that the P6 core actually executes. But there is not enough information released to date to know for sure. -------------------------------------- Re: "I don't think so. The x86 support comes from a separate x86 core included in a corner of the Merced chip." May I ask how you know this to be true? EP

To: Elmer who wrote (51772)	3/6/1999 11:56:00 PM
From: Cirruslvr	Read Replies (1) \| Respond to of 1573211

Elmer - RE: "Re: "I don't think so. The x86 support comes from a separate x86 core included in a corner of the Merced chip." May I ask how you know this to be true?" Maybe from this foil. theregister.co.uk