Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Tenchusatsu who wrote (51782)	3/7/1999 7:32:00 AM
From: dumbmoney	Read Replies (1) \| Respond to of 1573230

I don't know the details, but I'm pretty sure this is the case. Any IA-32 instruction gets fed into the little compatibility unit in the corner and gets translated into IA-64 instructions. I don't think it's much of a big deal compatibility-wise. The good ole P6 core translates IA-32 instructions into internal RISC-like instructions. Same thing with the K6 and the K7. Almost no one implements IA-32 instructions directly anymore. It's not that simple, though. On something like the P6, the micro-ops are designed to fit the semantics of x86 instructions, so there is a very direct translation between most x86 instructions and micro-ops. If you try to translate x86 instructions into, say, MIPS instructions, you find that even simple x86 instructions may require dozens of MIPS instructions to execute in conformance with full x86 semantics. It's messy and SLOW. I'm sure that the x86 engine uses at least some of the IA64 execution hardware - otherwise it would take too much die area. But the interface can't be all that neat.