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To: Tony Viola who wrote (75884)3/9/1999 12:32:00 PM
From: Scumbria  Read Replies (1) | Respond to of 186894
 
Tony,

If back to back, or serial (one driving another) latches update on the same clock cycle, you have a race. Very simple.

In the world of high performance microprocessors, it isn't that simple. Circuit designers frequently use asynchronous dynamic logic chains, in order to make the extremely short cycle times.

For example, it is nearly impossible to build the cache/TLB logic at speed completely in static logic. (Architects are starting to reduce the need for this sort of complicated circuitry by implementing deeper pipelines.)

This sounds as mysterious as AMD's last "explanation", which was a "mask problem."

AMD did not say it was a mask problem. They said it was "a speedpath which was fixed by a late mask change." Which makes perfect sense.

Scumbria