Materials play catch-up with lithography juggernaut
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Story posted 7:15 p.m. EST/3:15 p.m. PST, 3/17/99
By Anthony Cataldo
KYOTO, Japan - ( ChipWire/EET) -- The chip industry's drive to narrower line widths is blazing ahead faster than expected, leaving researchers devising new interconnect schemes and materials choking in the dust. The situation is putting new urgency into basic research to prevent the lithography juggernaut from being hobbled. But researchers warn that time is running out.
The dearth of new materials and processes came to light here recently at the International Forum on Semiconductor Technology, a gathering of researchers and consortia from major chip-making regions. Attendees admitted they were stumped over how the interconnect for advanced microprocessors would stay abreast of the accelerated lithography road map. And at least one major DRAM company, Hitachi Ltd., is predicting that gigabit DRAM production will have to be pushed out until new materials are developed.
Paolo Gargini, director of technology strategy at Intel Corp., said the industry may soon face the question of whether it is worthwhile to implement a new process generation. As lithography has shifted into high gear, the industry will in the next several years need to move to new copper interconnects, intermetal dielectrics and gate dielectrics that have not been developed.
"Between 100 and 70 nanometers, we don't know how to make it work," Gargini said.
In 1994, those narrow wavelengths were not expected to be ready for another 10 years. (As wavelengths get smaller, so does the width of a transistor.) This year, however, the Semiconductor Industry Association (SIA) is expected to announce a new technology road map showing those wavelenghts will be production-worthy in the next six years, according to presenters here.
The revised International Technology Roadmap for Semiconductors, a composite of projections from chip manufacturers in the United States, Europe, Taiwan and South Korea, is expected to show that an earlier version adopted just last year significantly underestimated the pace of lithography advances. "If you look at this you will see there are many corrections," Gargini said.
A cursory look at the preliminary road map shows just how far off the mark last year's revision was. Several presenters said the industry is expected to reach 125-nm wavelengths by 2001, or two years ahead of what was predicted last year. By 2003, 90-nm lithography is expected to be mainstream, three years earlier than the '98 road map showed. By 2005, the chip industry should have in place lithography tools to narrow the wavelength to 62 nm--four years ahead of the SIA's earlier schedule.
How did the industry get into such a predicament? The short answer is that chip makers have been obsessed for most of the 1990s with adopting the latest lithography as a competitive weapon, causing semiconductor R&D to become lopsided. A communications breakdown among chip vendors, universities and government-sponsored research labs has exacerbated the situation.
Observers here said Intel got the lithography ball rolling earlier this decade as it made a successful bid to outpace competitors in both the RISC and x86 camps. By the mid-90s, Intel superseded the DRAM industry in driving new lithography. In recent years, DRAM vendors have tried to come storming back, pursuing aggressive die shrinks to boost yields and cut costs -- sometimes with mixed success.
The result is an almost single-minded pursuit of lithography. There are currently seven "next-generation lithography" proposals being bandied about, and a raft of consortia in the United States, Europe and Japan overseeing development work. In an open forum on lithography here, panel members spent most of the time arguing about how to coordinate all the concurrent research projects.
Meanwhile, basic or "pre-competitive" research in materials and interconnect has fallen behind. This is because academia has been following old technology road maps born in the late 1980s, even as chip vendors have been notorious for trying to beat those road maps as soon as they are published.
"The benchmark is almost obsolete by the time you put it out," said Kenneth Monnig, associate director of the interconnect division at Sematech in Austin, Tex.
Development of low-k dielectric films, which are needed to prevent crosstalk between ever-closer transistors and metal layers in high-performance microprocessors, is one of the immediate concerns. Combining copper and low-k dielectrics is at the top of most chip makers' agendas for high-performance MPU and ASIC designs.
Copper interconnect has been successfully incorporated into process technologies, driven by companies like IBM Corp. and Motorola Inc., but low-k dielectrics have proven more elusive.
Low-k dielectrics have started to appear in new 0.18-micron processes, but their properties will have to undergo a radical change. Low-k films today have an effective dielectric-constant (k) rating of about 3.8, but soon they will have to move below 2.
Achieving that kind of dielectric constant means the material itself will become a porous, air-gel or foam-type substance that is not likely to have the same reliability chip makers have come to expect with time-tested silicon dioxide, observers here said.
Silicon dioxide has been used for decades as the primary insulating material for transistors and interconnects. But its k-rating is 4, so it will have to be replaced. The goal is to develop a new material with a much lower dielectric constant, along with all the thermal, mechanical, chemical and process attributes of silicon dioxide.
Paul Ho, a semiconductor researcher at the University of Texas at Austin, called that goal a "tall order," estimating that research is already 18 months behind schedule. He said the work that companies like IBM and Motorola have done in bringing copper interconnect into the mainstream provides only a temporary respite.
"Copper buys time for future development of low-k dielectric," Ho said. "The disadvantage is that when you move back this material development, you push up demand later on and make it tougher to integrate."
Part of the problem stems from a misunderstanding between the industry and academia. According to Monnig of Sematech, many universities had been following the Micro 2000 road map published in 1991 by the National Advisory Committee on Semiconductors, a report now considered obsolete. Research into new semiconductor materials has lagged as a result.
"We've used silicon dioxide since Bob Noyce patented the wiring of aluminum transistors," Monnig said. "Moving to copper plus low-k is not going to provide another 35 years of interconnect. Perhaps it will be only two or three years, then to maintain the performance curve you're going to have to move to even more radical solutions that nobody knows. People are talking about superconductors or optical interconnections, but those are going to take a long time to develop."
The search for new low-k dielectric films is just one of many interconnect-related issues the industry has yet to conquer. Two years ago, those "red zones" were not on track to appear until 2009, when lithography was expected to reach 70 nm. Now that schedule is expected to be pulled, sending researchers scrambling to find production-worthy solutions. Major interconnect issues include:
devising a way of cramming up to 10,000 meters of interconnect into a single device;
increasing the reliability of logic transistors by an order of magnitude;
grappling with larger logic, DRAM and via aspect ratios;
reducing resistivity;
narrowing the barrier thickness to 8 nm.
Sematech is collaborating with universities, chip makers and various national laboratories to devise a new interconnect road map this year, Monnig said.
Ho said 30 low-k materials are being investigated now. One possible avenue is to start with a silica-based material and then introduce porosity. Ho said this type of material, which is 50% porous, yields a 2-k rating. Another approach being taken by IBM is to employ a hybrid co-polymer material, He said.
DRAM vendors are also grappling with the void in materials research. As memory-cell sizes shrink to less than 0.5 micron2, the DRAM industry will need new materials for isolation diffusion regions for source and drain, interlayer dielectrics, interconnect and wiring. With system-on-a-chip integration, the gigabit DRAM will also need new materials such as BST or PZT to keep stacked-capacitor structures in check.
On another front, semiconductor makers will have to pursue parallel research into advanced packages to house the new ICs.
"Otherwise it will be like putting a Ferrari engine inside of a pickup truck," said Ho. "Low-k chips will have serious problems with wire-band and wire bonding," he said. "New structures and new processes will create thermomechanical problems so that the packaging will have to be different too."
He said that the most likely outcome will be a flip-chip type of package with wire bands running laterally within the top and bottom layers of the capsule.
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