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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: kash johal who wrote (52951)	3/19/1999 2:00:00 PM
From: Tenchusatsu	Respond to of 1579241

Kash and all, some Dilbert humor: Sorry to beat a dead horse, but I just thought this was pretty funny. This came from the desk of one of my team leads: Dilbert: I have an ethical question, Dogbert. Dogbert: I'm here to help. Dilbert: Is it better to give customers a low quality product in a timely fashion ... or is it better to lie about product availability until the bugs are fixed? Dogbert: I will need my assistant, Ratbert, to address your ethical question. (Ratbert strolls in next to Dogbert) Dogbert: Let's say Ratbert is a trusting and innocent customer. Suppose somebody abuses his trust like this ... (Dogbert pushes Ratbert over the edge of the couch. SPLAT!) Dilbert: How does this relate to my situation? Dogbert: To be honest, I wasn't listening to you. Sound familiar to anyone? Tenchusatsu

To: kash johal who wrote (52951)	3/19/1999 2:09:00 PM
From: Shane Geary	Respond to of 1579241

Re: " I take it to mean they are either going to use SDC or Mot.while fab 30 ramps." In an ideal world, for huge volume parts (ie MPU, DRAM, SRAM etc), the process and the part are designed together. You don't develop a process and then design parts for it. That's what foundries and ASIC fabs do. For MPUs/DRAM etc, the development of both is (or should be) combined. That way, the performance, cost, yield and reliability of the process can be maximised. For that reason, it isn't easy to switch a design from one process to another even if both are optimised for high-speed CMOS (and even if the layout/design rules are the same (big if)). Look at how long the IBM/AMD foundry partnership existed without any chips being sold. A lot of work would have to go into making the K7 compatible with, say, IBM's CMOS 7S process. Some design tweaks and iterations through the fab would be required - all takes time. Bottom line: don't expect MOT/IBM K7s any time soon, if ever. Unless AMD secretly transferred Motorola's entire process, not just the Cu interconnect technology. The SDC is a pilot line - how many wafer starts can be dedicated to the K7? Does it have the metrology equipment to sustain a lot of wafers?