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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Tony Viola who wrote (53211)	3/22/1999 5:36:00 PM
From: Scumbria	Respond to of 1583318

Tony, Still, I don't get how, given two designs that have reasonably close clock speeds, the one with a three cycle cache access is better than one with two. 'Splain? The standard microprocessor implementation uses two cycles to do these tasks: address calculation - Clock 1 phi 1 address translation - Clock 1 phi 2 cache lookup - Clock 2 phi 1 cache data access - Clock 2 phi 2 As clock speeds and L1 cache sizes have increased, this has become too difficult. Your assumption of all synchronous design is not valid, because it is impossible to do this synchronously at high MHz. TLB's and L1 caches typically use some self-timed asynchronous logic. The Alpha architects bit the bullet and threw in an extra clock to accomplish these 4 tasks. This removed the fundamental speedpath which limits PPC, K6, and M1 core clock speed. (I almost threw P6 into the list, but Ten has questioned me on this so I need to do some research.) Scumbria