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Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: Al Serrao who wrote (17955)	3/29/1999 9:35:00 AM
From: REH	Respond to of 93625

LSI Logic Launches Direct Rambus ASIC Cell CoreWare PR Newswire, Monday, March 29, 1999 at 09:19 Test Chip Functional at Full 800 MHz Speed MILPITAS, Calif., March 29 /PRNewswire/ -- LSI Logic (NYSE:LSI), The System on a Chip Company(R), announced today that it has shipped CoreWare(R) models for the Direct Rambus(TM) ASIC Cell (D-RAC) in the LSI Logic G11(TM) process technology (0.18-micron Leff) to customers. In addition, LSI Logic's D-RAC test chip is functional at the full 800 MHz speed. Consistent with LSI Logic's methodology for CoreWare developments, the D-RAC core undergoes a thorough process of silicon verification and qualification. LSI Logic's solution supports the Direct Rambus specification and is a key addition to LSI Logic's portfolio of industry-leading high-speed I/Os which includes the GigaBlaze(R) and HyperPHY(TM) cores. The D-RAC addition to the CoreWare library reinforces LSI Logic's leadership in high-speed I/O and the company's long running expertise in Rambus design implementation. "In a market where development time is critical, we needed a semiconductor partner with a proven methodology and a track record of successful applications/core integration," said Lisa Brown, research and development project manager for HP's ProCurve Networking division. "With LSI Logic's D-RAC, we have the benefit of comprehensive support and LSI Logic's experience in high-speed I/O combined with a high-performance solution that is easy to integrate." With signal pin rates of up to 800 megabits per second, Direct Rambus technology uses a two byte wide data path to achieve peak data rates of 1.6 gigabytes per second and is one of the highest performance memory interfaces available. Combining high bandwidth and extremely low pin-count, the D-RAC addresses the high-speed memory requirements for a range of applications from consumer electronics to high-performance computer desktop systems. By integrating multiple D-RACS onto a single ASIC, customers can reduce pin count and lower cost. "Major players in multiple market segments are adopting Rambus technology, and we expect widespread usage in the near future," said Marc Miller, product marketing director, LSI Logic. "We have been working with Rambus technology for four years and are offering a comprehensive set of tools and support for our D-RAC core. Combining this D-RAC interface with other cores from our CoreWare library enables our customers to reach the marketplace with leading-edge products and reduced time to market." "As a recognized ASIC leader in high-performance I/O, LSI Logic is a key Rambus partner as we move towards widespread adoption of Direct Rambus technology," said Subodh Toprani, vice president and general manager of Rambus' Logic Products Division. "We've had a close working relationship with LSI Logic and are impressed by their strong commitment to Rambus technology to ensure customer success in implementing the technology." LSI Logic, a licensee of Rambus technology, is currently working with leading companies that are integrating the D-RAC cores in their ASICs for different market segments. These applications span from computer chipsets to network switches, to printers. The D-RAC core is LSI Logic's third generation of Rambus technology, having first offered Concurrent RACs several years ago in its 0.5-micron process technology. For integration of the D-RAC core into an ASIC, the CoreWare deliverables include a behavioral model, synthesis and timing models and a system verification environment. Looking forward, LSI Logic is working to continue to meet its customers' memory interface needs by offering Rambus technology in future generation CMOS process technologies. Coupled with LSI Logic's existing high-speed I/O capability, the D-RAC core enables ASICs with very high bandwidth ports to utilize Rambus technology's high-performance memory interface. For example, ASIC designers may combine LSI Logic's GigaBlaze Cores for standards compliant multi-gigabit serial interconnects or HyperPHY Cores for multi-gigabyte backplane interconnects with the D-RAC core for a high-performance memory interface. In addition, LSI Logic offers a full line of buffers including CPU front-side bus, AGP and PCI buffers to meet system requirements. reh