Toshiba to Reduce 64 Megabit DRAM Production by Nearly 90 Percent by Year-end
IRVINE, CALIF. (April 1) BUSINESS WIRE -April 1, 1999--Toshiba America
Electronic Components Inc. (TAEC), a North American subsidiary of
Japan's Toshiba Corp., Thursday announced Toshiba's plans to
substantially cut 64 megabit (Mb) DRAM production by the end of this
year, shifting the majority of its DRAM output to 128Mb SDRAM and other
high-performance memory, including Rambus(R) DRAM (RDRAM(R)) and
Double-Data-Rate (DDR) SDRAM.
Toshiba's latest plans call for reducing 64Mb DRAM production down to
one million pieces per month by December 1999.
In response to customer demand, Toshiba will accelerate the output of
128Mb 133 megahertz (MHz) SDRAM, DDR SDRAM and RDRAM. The company can
support this high capacity of high-performance memory because of its
scalable design approach and rapid transition to 0.20 micron(um)
process geometries. This process enables efficient volume production of
133MHz SDRAM, 800MHz RDRAM and other high-density memory solutions.
By June, Toshiba's flagship Yokkaichi Works DRAM facility will be
processing wafers at 0.20(um) for 100 percent of its DRAM production.
By August, Dominion Semiconductor in Manassas, Va., will have
transitioned its output to 0.20(um), and the majority of Toshiba's
dedicated production at Winbond, in Taiwan, will also be at 0.20(um).
"Upgrading effectively all of our DRAM production to the 0.20(um)
geometry by the end of the third quarter, and focusing on 128Mb-based
memory solutions for servers, work-stations, high-end PCs and notebook
PCs, enables us to provide the greatest added value to our customers,"
said Jamie Stitt, DRAM business development manager at TAEC. "This
change is being driven by market demands for high-density and
high-performance DRAM. Toshiba was the first manufacturer to produce
128Mb SDRAM at a 0.20(um) process geometry, and is one of a very small
number of manufacturers shipping 128Mb devices in volume."
Further plans call for the transfer of Yokkaichi's 0.175(um) pilot line
technology to mass production lines beginning in the fourth quarter
1999.
"Initially, our emphasis will be on 100 and 133MHz SDRAM, and will
include RDRAM and DDR SDRAM as demand grows," Stitt continued. "Whether
the industry demand is for 133MHz SDRAM, 800MHz 128/144Mb RDRAM or
266MHz DDR SDRAM, Toshiba will be able to respond within the normal
production cycle-time. All of these high-performance products are
designed with the same 0.20(um) process, and can be manufactured at any
of Toshiba's global network of fab facilities."
"DRAM manufacturers are saddled today with difficult choices, mainly
requiring them to enhance processes and change interfaces at an
accelerating rate, at a time when investment capital is difficult to
obtain," said Jim Handy, principal analyst, Dataquest. "Companies need
to align themselves with tomorrow's bestselling products, for example
fast interface DRAMs like Rambus, PC133, or DDR, and the 128Mb density
to assure that they will make it through 1999 and emerge in a
leadership position."
Toshiba offers 128Mb SDRAMs based on 0.20(um) CMOS process technology
in three organizations (32Mb x 4, 16Mb x 8, 8Mb x 16) and two speeds
(100 and 133MHz). Toshiba's 128Mb DRAM utilizes the trench memory cell
design that resulted from the IBM-Siemens-Toshiba joint development
project for 256Mb DRAM, which contributes to the reliability and power
efficiency of the memory devices. Toshiba's newest 133MHz SDRAM modules
and components are targeted for use in high-end servers and
workstations with next-generation processors that feature bus speeds of
133MHz.
"Toshiba's high-performance 512MB 133MHz SDRAM modules have passed our
initial qualification tests," said David Pulling, vice president of
marketing for Reliance Computer Corporation (RCC), a leading chipset
supplier developing faster bus speed solutions. "The company's plans to
transition their entire DRAM output to this advanced process positions
them to become a leader in the 133MHz DRAM arena." Toshiba has already
sampled 133MHz SDRAM and 800MHz RDRAM, and separately announced today
that it is sampling 128Mb DDR SDRAM.
Scalability
Toshiba has long been a leader in memory technology. The company's
mastery of design and manufacturing processes stems from a modular
scheme Toshiba calls unified design architecture (UDA) and unified
design rule (UDR). Using DRAM as a process driver, UDA/UDR allow almost
any VLSI device to be constructed in building-block fashion during
manufacturing. Over the years, Toshiba achieved industry leadership
from this core competency; today, it is known as Scalable by
Design(TM). Harnessing advances from the trench cell-based 256Mb DRAM
development project and applying them to the 64Mb and 128Mb densities,
Toshiba can seamlessly scale five generations from 0.35(um) to 0.15(um)
with one clean room. With necessary investments and major technological
hurdles overcome at the 0.35(um) geometry, only an additional modest 10
percent investment is required for each microlithography refinement.
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