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To: Process Boy who wrote (77652)4/2/1999 5:53:00 PM
From: Paul Engel  Read Replies (2) | Respond to of 186894
 
Process Boy - Confirmation that Whitney Chip sets contains Portola Graphics engine.

The following article describes some confusing issues regarding Intel's near-term Chip Set road map.

But it does confirm that the upcoming Whitney chip set - with integrated 2D/3D graphics - is based on the new Portola Graphics engine, NOT the older i740 engine.

"The Intel 810 and the new Intel 810E will integrate a derivative of the i752, Intel's next- generation Portola core, and not its existing i740 graphics chip, as once thought. Both chipsets will support a unified memory architecture Intel calls Dynamic Video Memory, as well as dedicated PC-100 SDRAM."

The remaining issues seem top be centered around Rambus/Camino Delays and 100 vs 133 MHz SDRAM options.

Paul

{================================}
Intel veers from IC roadmap

By Mark Hachman, Electronic Buyers' News
Apr 2, 1999 (2:02 PM)
URL: ebnews.com

Silicon ValleyThe uncertainty surrounding Direct Rambus DRAM has again jostled Intel Corp.'s chipset roadmap, threatening to unseat the stable platform the company hopes to establish. OEMs are being notified that the chipset once known as the Intel 815 has been renamed the Intel 810E, offering low-cost PCs a 133-MHz frontside bus by September-three months earlier than the original shipping date of the Intel 815.

That has complicated Intel's chipset roadmap, which was supposed to be relatively straightforward. At Intel's fall analysts conference, company executives had promised a simple 1999 chipset lineup, minimizing the qualification testing OEMs needed to perform on each device.

Ideally, that meant OEMs would choose from only three desktop-PC chipsets-one each for low-end, midrange, and high-end PCs.

According to the roadmap outlined in late 1998, Intel would have introduced both the Intel 820 (Camino) chipset for high-end PCs and the Intel 810 (Whitney) chipset for low-end, Celeron-based PCs. Both releases had been scheduled for the first week of May. The 815, meanwhile, was aimed at the midrange market.

But the unexpected delay of the Camino until September has complicated matters. OEMs say that instead of three chipsets by the end of the year, six could coexist: the new Intel 820, 810, and 810E, plus the older 440ZX and 440BX, and even the 440LX.

A spokeswoman for Intel in Santa Clara, Calif., declined to discuss future products. But one customer said his company is coping with the roadmap revisions. "We're used to it," he said. "It's been that way for the past year."

The Intel 810 and the new Intel 810E will integrate a derivative of the i752, Intel's next- generation Portola core, and not its existing i740 graphics chip, as once thought. Both chipsets will support a unified memory architecture Intel calls Dynamic Video Memory, as well as dedicated PC-100 SDRAM.

The features of the various chipset families add still more wrinkles. The frontside bus of the 440BX and Intel 810, for example, can run at either 66 or 100 MHz, while the Intel 820 and Intel 810E can run at either 100 or 133 MHz, according to sources and Intel's confidential documentation. And a rumored 440BX2 chipset would even add 133-MHz frontside-bus capabilities to the BX platform.

"If the Pentium III is to reach 700 MHz by the end of the year, the processor bus has to run at 133 MHz, or else the system performance drops," said another Intel customer, who requested anonymity.

Even so, the introduction of all three chipsets will likely be beat by Via Technologies Inc., which sources say will sample its Apollo Pro Plus 133 chipset for a 133-MHz P6 bus early next month. Executives at Via's U.S. operations in Fremont, Calif., declined to comment.

Confusing the chipset roadmap further is the fact that Intel has reapplied the Intel 815 moniker to yet another chipset shipping at the end of the year, according to two OEMs. The 815 label is being applied to a chipset that integrates the Coloma, Intel's third-generation graphics chip, to be introduced in May, sources said. Alleged problems integrating the graphics core forced a delay as well as the name change.

Intel's DRAM roadmap is only slightly clearer: By the end of 1999, Direct RDRAM will be included in high-end PCs, with PC-100 SDRAM in lower-end machines.

The problem is that the Intel 810E, as a low-end to midrange chipset, falls somewhere in between the low and high ends of the PC spectrum. According to industry sources, Intel has scheduled the chipset's September launch opposite the Intel 820 for lower-performance PCs. Like the Intel 820, the Intel 810E adds a 133-MHz frontside bus.

But while the Intel 820's 133-MHz bus interfaces to Direct Rambus DRAM, Intel has not broadly specified a memory interface for the Intel 810E. Only two of five sources indicated that Intel will mismatch a 133-MHz processor bus with a 100-MHz memory interface to PC-100 SDRAM. "It doesn't make sense to me either," said a senior executive at one motherboard manufacturer. "But our thinking is that there may be some performance advantage in tying together the processor and graphics in this fashion."

Intel apparently has not changed its position against support for the PC-133 SDRAM interface.

"History says, if Intel introduces a new memory interface for a chipset, they'll send a preliminary specification out to suppliers very early on," said Kevin Kilbuck, manager of memory engineering for Toshiba America Electronic Components Inc., Irvine, Calif.

Observers speculated that any reversal of policy on Intel's part would likely come at the end of the year, when the PC-133 interface is expected to be well established.

Additional reporting by Jack Robertson, Andrew MacLellan, and Sandy Chen.



To: Process Boy who wrote (77652)4/2/1999 5:57:00 PM
From: Paul Engel  Read Replies (1) | Respond to of 186894
 
Intel Investors - Another possible GLITCH in RAMBUS DRDRAM memories.

This one seems like it should have been caught LONG AGO - as it is a basic LOGIC FAULT contained within the internal logic cells of DRDRAM memory.

Camino and DRDRAM introduction schedules may further slip - but Samsung seems to have already corrected the problem in their Rambus memory chips.

Paul

{================================}
Suppliers battle Rambus bug
By Jack Robertson,
Electronic Buyers' News Apr 2, 1999 (2:05 PM)
URL: ebnews.com

Intel Corp. has discovered a flaw in the Direct Rambus DRAM interface that could force some chip companies to implement an extensive hardware fix across their device-mask layers, a broad range of industry sources said last week. Several major DRAM makers said privately that in a worst-case scenario-if they are forced to make an unscheduled revision to their mask sets-it would take three months to bring the new iteration to silicon and another three to test and qualify the chip.

The bug, called a "CMOS truncated bit," causes the memory data reading to the DRAM registers to shut down, according to messages Intel sent to chip suppliers in the past two weeks. This is because the leading edge of the clock cycle terminates the register read-just the opposite of what must happen to transfer data.

Samsung Electronics Co. Ltd., which is expected to manufacture much of the Direct RDRAM produced in the industry this year, acknowledged the bug but called it a non-issue. "Samsung's Rambus is fully functional and has been demonstrated to work in fully stable systems," said Avo Kanadjian, vice president of marketing for Samsung Semiconductor Inc., San Jose.

Spokespeople and executives for three other DRAM companies-LG Semicon Co. Ltd., NEC Corp., and Toshiba Corp.-said they've received no communiquĊ½ regarding a Rambus flaw within the past few weeks. Toshiba, however, said it discovered a bug two months ago, since fixed, that triggered a power spike during Direct RDRAM's power-up sequence.

Intel discovered the latest problem when testing Direct RDRAM chips with its Camino chipset, according to sources. In an interview last week, Howard High, Intel's director of corporate communications, would not confirm the existence of the bug specifically, but said such discoveries are not uncommon in a new product as advanced as Direct RDRAM.

A spokeswoman for Rambus Inc., Mountain View, Calif., said she had no knowledge of any deviant register bug in Direct RDRAM.

However, David Pulling, vice president of marketing for chipset maker Reliance Computer Corp., Santa Clara, Calif., said some DRAM suppliers told him last week that they may yet have to implement an all-layers mask redesign. Most chip makers interviewed for this article declined to comment for attribution, citing contract terms with Rambus that bar them from making critical statements.

Analyst Sherry Garber of Semico Research Corp., Phoenix, added that PC OEMs had voiced concern to her about a Direct RDRAM mask redesign. And Danny Lam, director of Fisher-Holstein, a semiconductor consultancy in Wilmington, Del., said clients have told him of the problem, which he said could be significant.

According to sources, Intel told DRAM makers that they would shortly receive revised engineering specifications from Rambus to remedy the problem.

Samsung said Intel notified it of the bug, which issues a "0" instead of a "1" during the DRAM's initialization sequence, but recommended a temporary, system-level software fix. Intel then advocated a hardware redesign during the next regularly scheduled Direct RDRAM die shrink, allowing companies to avoid the time and expense of an added mask-set revision.

"Such a communication [was made by Intel], and indicated that there was a system-level work-around in place," Kanadjian said. "When the next planned die shrink is introduced, there was a recommendation that the change to Rambus be made then."

Other memory companies surveyed last week said customers may be disinclined to accept a software bandage, and may require their suppliers to make a forced mask-layer revision to correct the problem in hardware.

The change, though relatively small, would require a redesign of logic functions on the Rambus chip and could entail an all-layers mask redesign, they said. Even the smallest revision, if it involves making new masks for each of Direct RDRAM's 16 to 20 layers, would take three months to implement in silicon, and another three to qualify, chip makers agreed.

In the event of such a delay, suppliers could still get a redesigned and qualified Rambus chip to market in the late fall, about the same time as the revised timetable set by Intel for introducing its Rambus-enabled Camino chipset.

However, Semico's Garber said the bug only creates more uncertainty in the market for Direct Rambus. Many PC companies are now negotiating with Reliance Computer and Taiwan-based independent vendor Via Technologies Inc. for supplies of alternative chipsets, she said. Rather than adopt Direct RDRAM, Garber said, chip makers may be tempted to turn to PC-133 SDRAM to fill the gap caused by the Rambus delay.

Additional reporting by Andrew MacLellan.