To: Yougang Xiao who wrote (54009 ) 4/5/1999 1:08:00 PM From: Shane Geary Read Replies (1) | Respond to of 1571259
Re: "Could you two please shed lights as to what are the significances of the HIP5L or HIP6L process in relation to copper thing at Fab 30?" I don't have much knowledge of Motorola's processes, and couldn't find a whole lot on the web. I looked at the International Electron Devices Meeting proceedings for the past few years but couldn't be sure that MOTOs papers were referring to HIP5L/6L. HIP stands for HiPerMOS, or High Perfomance CMOS - Motorola's name for their new CMOS processes. I wonder does 5L stand for 5 levels of metal? Maybe not. From the original press release: "Copper interconnect technology is necessary to continue to increase processor speed and performance and represents a key element in our 'Gigahertz 2000' goal," Sanders continued. "Our first co-developed logic technology, HiPerMOS 6L, will enable us to produce gigahertz AMD-K7(TM) microprocessors in our Dresden megafab in the year 2000. Collaborating with an industry leader such as Motorola will put AMD on equal footing with the best of the best in logic process technology and in the lead in embedded flash memory technology." In a previous post (#52954 when, in my ignorance, I thought that the AMD/Motorola deal covered copper only) I said: "...it isn't easy to switch a design from one process to another even if both are optimised for high-speed CMOS (and even if the layout/design rules are the same (big if))" "Bottom line: don't expect MOT/IBM K7s any time soon, if ever. Unless AMD secretly transferred Motorola's entire process, not just the Cu interconnect technology." So, I guess it is essentially HIP6L that is being semi-transferred into Fab30 (hard to transfer a process that's not yet fully developed). So I guess I was kinda wrong and kinda right? On a different note, from a quick back of the envelope calculation, I think that AMD can fit about 130 K7 die per 8" wafer on the 0.25um process.