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To: Paul Engel who wrote (78491)4/12/1999 12:53:00 AM
From: Scumbria  Respond to of 186894
 
Paul,

No matter how the cache is implemented, 3 clock cycles is 3 clock cycles.

L1 cache access on K7 has the same latency as the world's fastest CPU- the Alpha 21264. The effect of the extra clock cycle is minimal.

If the pipeline is kept full, the effect is zero.

Scumbria