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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Scumbria who wrote (55661)	4/15/1999 8:35:00 PM
From: Tenchusatsu	Respond to of 1576858

<It is kind of silly to try to extract huge amounts of bandwidth out of a single DRAM across a single bus.> I can only speak from the viewpoint of servers, where you extract huge amounts of bandwidth out of multiple DRAM modules. Notice how two of the controllers I mentioned, Gigabit Ethernet and RAID SCSI controllers, are not going to appear on your next E-machine. But even devices like graphics cards which have its own frame buffer and texture memory onboard can benefit from Direct Memory Access. When it comes time to download textures into the card's onboard memory, it's less CPU-intensive to have the card copy the textures directly from memory, instead of having the CPU write directly to the card. In either case, the texture data is sourced from DRAM, so DRAM bandwidth is being consumed anyway. Of course, you can avoid going to DRAM in the first place by having the CPU read each chunk of data from the hard drive controller, then writing it to the graphics card's local memory. But you can imagine how extremely CPU-intensive this will be. Or you could have the graphics card do peer-to-peer accesses to the hard drive, but that's even more difficult. In any case, all data is being sourced and dumped to and from DRAM, even data that's going to end up on the local frame buffers of a graphics card or disk controller or Ethernet card. That's why the limiting factor isn't the processor-to-chipset pipe, but the chipset-to-DRAM pipe. Tenchusatsu