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Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: Dave B who wrote (19117)	4/24/1999 10:37:00 AM
From: Bilow	Read Replies (1) \| Respond to of 93625

Hi Dave B; Regarding those Rambus voltage swings and FPGAs... Direct Rambus has a Vref compliance range of 1.2 to 1.6 Volts, and a voltage swing range of between 0.4 and 1.0 volts. Here's Rambus's spec for the Direct Rambus: (pdf 1.138MB) rambus.com Xilinx's Virtex supports some low voltage swing logic families. They give you LVTTL, LVCMOS2 (i.e. LVTTL_2), PCI, GTL, GTL+, HSTL I, HSTL III, HSTL IV, SSTL3 I, SSTL3 II, SSTL2 I, SSTL2 II, CTT, and AGP. Of these, the one I would be most likely to try and hook up to Rambus would probably be SSTL2, as it is available in a lot of choices of drive strength & slew rate. Here's Xilinx's spec for how to program Virtex I/O pin types: (pdf) xilinx.com You can see that there are no direct matches to Rambus's Vref, Vtt and logic levels. A convenient web reference (non-pdf) for SSTL2 specifications is available as part of IBM's on-line specification for its 256M DDR SDRAM: chips.ibm.com This is not the location of the official SSTL2 spec, but it is the one I could find quickly. Amusing side note: The SSTL2 spec requires that the internal positive supply voltage of SSTL2 compliant parts be no greater than the I/O supply voltage. I am not sure why this requirement is there, and the DDR makers probably aren't either, as most of them violate it. The Vref compliance for SSTL2 turns out to be 1.15 to 1.35V. This is compatible with Rambus, particularly, Vref from 1.2 to 1.35V could be used. Further perusing of the spec reveals that the SSTL2 logic swing is +/-0.35 for AC signals, (i.e. to initiate a change in logic value), and +/-0.18 for DC signals (i.e. to insure continuation of that value.) While a minimum voltage swing on Rambus is not going to be a valid logic swing for SSTL2, due to the AC specification, the DC specification is fine. So it might be possible to hack together something to allow communication between the logic families. I have some ideas, but given the consideration that some future employer might doubt my sanity, I will refrain from posting them in a public place... On the other hand, about the fastest you are going to get data out of an FPGA is 250MHz, and this speed is achievable with DDR. Since Rambus, in this instance, gives you no advantage in bandwidth, and has a more difficult interface, it's pretty easy to choose DDR (which use SSTL2 or LVTTL). -- Carl