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To: Dave B who wrote (19508)	4/29/1999 2:43:00 PM
From: Tenchusatsu	Respond to of 93625

<One last question -- is there any current real-world scenario to which this analysis could be applied? Workstations? Low-end or single-processor servers? High-end or mutliple-processor servers? Anything? What situation do you suppose they had in mind when setting up their test scenario?> Well, they did try to "even the playing field" by pitting one RDRAM channel against two PC100 SDRAM channels. And two PC100 SDRAM channels can support four DIMM slots each, for a total of eight DIMMs. The RDRAM channel can only support four RIMMs. That means the two PC100 SDRAM channels can support more memory than the RDRAM channel, and it can match the peak bandwidth of RDRAM, although it isn't going to be as efficient in utilizing that bandwidth. Yet for servers, it's more important to be able to support huge amounts of memory, such as 512 MB or even 2 GB. Supporting that much memory with RDRAM channels will be overkill in bandwidth and very expensive. It's better to just support that much memory with SDRAM channels, and work those channels in parallel to create a very wide memory path. There's another problem with the test scenario that the research paper created. It's trying to simulate system performance by simulating single applications on a theoretical superscalar processor. This sort of simulation ignores traffic coming in from PCI peripherals or AGP graphics controllers, because you just can't simulate that on their toolset. Plus, it's unlikely that they were able to simulate more than 15 seconds of real runtime per test. Finally, because they only simulate one application at a time, it's possible that the processor caches reduced the memory traffic by a very significant amount. In other words, the simulation is too far away from the real world to mean anything. Intel does a lot of performance tests using hardware performance counters in their processors and in their chipsets. They'll run real applications (as opposed to simulating them) on real systems with real devices, then use their hardware counters to measure performance data. The only problem with this method is that by the time you find a bottleneck in performance, it might be too late to change anything before production. In short, performance analysis is much more complicated than this research paper makes it out to be. But the paper does make a lot of valid points, such as the importance of latency, the fact that RDRAM is much better at randomized accesses than SDRAM, etc. Tenchusatsu