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Technology Stocks : Altera -- Ignore unavailable to you. Want to Upgrade?

To: Sylvia Dupuis who wrote (2032)	4/29/1999 9:38:00 PM
From: schlep	Read Replies (1) \| Respond to of 2389

Sylvia, sounds like you are a marketing person working for Lattice or possibly Vantis.? Not a bad guess considering the cheerleading and lack of due technical diligence. Your impressions of LUT performance are very aged. New generation LUT performance have ~1.0ns tpd thru the LUT. Add in some localized routing (either segment or local interconnect) for another 0.6ns and you can begin to see that despite being more granular, the LUTs can actually surpass CPLD performance even for wide functions.!! Here are multiple examples: 32bit CRC (3 levels 10 lcells), 32 bit Adder (32 lcells), deep Multiplexors (10 lcells,2 levels for 16:1), Even address decodes, and State Machines (1hot encoded). Newest generation FPGAs can actually hack it believe it or not. What makes you think that the CPLD business is growing? Mcells shipped to the industry has surely increased, Revenue for CPLDs has been falling in the industry leaving a relatively flat line of constant dollars(check Dataquest). Lattice did however see flat revenus as their mixture of splds decreased while their cplds increased. Vantis however, I am not so sure saw that trend as their total revenue has been in decline. Max probably still pays the bills at Altera but I truly think that Flex product at their incredibly high growth rate (both LUTs shipped and Revenue) will cross over Max revenue sooner than you think - that at least is what Altera is publically projecting. Lastly, for you and Lewis - currently IO is the pure bottle neck for all programmable logic. Debating Frequencies of much over 100mhz is almost comical. Tsu's are running ~3ns and Tco's are running ~4ns so as you can see IO performance is pretty much limited to just over 100mhz. Even Tpd requirements of <7ns can now be met with Virtex or Apex for fast asynchronous requirements. That's about all, you can bet on your horse Lattice, Lewis and I will keep our bets on Altr and Xlnx to place and show. Thanks for the discussion. -schlep

To: Sylvia Dupuis who wrote (2032)	5/3/1999 12:32:00 PM
From: Lewis M. Carroll	Read Replies (1) \| Respond to of 2389

Sylvia, your arguments show that you know something about CPLDs. Here's my argument: 200 MHz allows 5ns. That's three levels of on-chip logic in Virtex. Using all four LCs and local CLB routing allows, for example, an address decode of 13 address bits in 2.5ns. Take four of those and add a single LUT-4 in a fifth CLB and you pay +1 ns for routing, +1 ns for the LUT but you now have 52 (4 x 13) address bits in 5ns. That beats CPLDs. No, I'm not counting I/O pad delays - this is all on-chip. In the real world, you may have to get on the chip, do your decode and get back off in <5 ns. That limits you to only the smallest of CPLDs. If it's get on chip, do your decode and register the result then get off-chip, you still are limited to smaller CPLDs but Virtex can meet this (doing it now on a critical path for 64 bit 66MHz PCI). Remember, CPLDs get slower as they get bigger (not true with FPGAs - maybe 10K we'll see about 20K). Show me a big (>200 cell) CPLD without limited routing (Cypress 39000 has limited routing - looks like an FPGA with big CPLD CLBs instead of X/A LUT4 CLBs) that can do a wide function at 200MHz... Also, all CPLDs are limited in speed first by their block fan-in (<20 for Lattice, Vantis, 36 for Altera, Cypress, 54 for Xilinx), and second by the number of dedicated PTerms per macrocell (Cypress is best here at 16, Lattice at 4, Altera, Xilinx at 5, Vantis at 4 I think). There are various schemes for increasing product terms used by a macrocell (parallel expander, shared expander, etc.) but all incur a timing penalty. Your fundamental argument is that LUTs cannot handle wide functions well and must be cascaded. True, but Virtex allows you to do just that at blinding speeds - my argument. How do you define "Logic efficiency?" Compare prices - FPGAs give you far more logic per dollar than CPLDs. It's almost universally true that if you can do the same function in either an FPGA or a CPLD, the FPGA function will cost less (given that an equal price FPGA and CPLD is available). P.S. You wouldn't be Ed using your wife's account would you?