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Technology Stocks : Energy Conversion Devices -- Ignore unavailable to you. Want to Upgrade?

To: Retiarius who wrote (3609)	4/30/1999 7:22:00 PM
From: Allen Bucholski	Respond to of 8393

EV still requires 10% sales in 2003 California's mandate. Off the wire service. dailynews.yahoo.com Allen

To: Retiarius who wrote (3609)	5/1/1999 10:21:00 AM
From: fred whitridge	Read Replies (1) \| Respond to of 8393

Retiarius, Welcome back. No mention of magenesium at the annual meeting that I recall and in fact all has ben quiet on that front of late. Yes, definitely the hybrid and SLI batteries would get kettering humming. Would be very interesting to know where two EV packs a day are going, since Devlin et alia aren't able to get their hands on a NiMh EV1.

To: Retiarius who wrote (3609)	5/8/1999 1:33:00 AM
From: Retiarius	Read Replies (2) \| Respond to of 8393

ORAM -- it all comes down to cost per bit my back-of-the-envelope calculation is that ORAM must hit the market (for any application) at less than twice the cost per bit than straight FLASH. why? because it's hard to imagine a system needing both fast access (read/write/erase) and nonvolatility which can't be simulated by a dual DRAM/FLASH combination. technically, to get both without ORAM, just do all fast access and updating using N-bits of standard cheap DRAM, then "snapshot" the state to a mirror image of N-bits of FLASH every so often. as long as that "so often" is less than the 100K life cycles of flash (say a car engine start/shutoff), it's okay. since both DRAM and FLASH are similar cost per bit for large N (0.18-0.25 micron process), ORAM must abide at cost <2N. already there are dual static DRAM/FLASH chips on the market for such purposes. what this means per ECD is that it can't enter memory niche markets at an arbitrary high price (what price new functionality?) ala what GMO is propagandizing for pure EV batteries. however, if ORAM can join the memory rat race at sub-0.2 micron at cost per bit less than FLASH, then it'll be blood in the streets. i can see why t. lowrey wants to go for embedded system RAM first, because it might just be a similar 25% process cost increment for an extra 3-5 process steps as IBM claims for combined embedded (volatile) DRAM and logic. if ECD hits the same stride and can also offer nonvolatility here, then they can save chip area from having embedded FLASH, as long as that all-to-critical cell area is submicron. multibit could be key here, but already FLASH (NOR process nordham-tunneling? i dunno, ask lowrey!) comes in at 2-bits (4-states) per cell. my own admittedly biased state is one of optimism in the face of ramtron's ferroelectrics (FRAM -- see March 8 Forbes piece), or IBM's magnetic spin valves (recent Scientific American). it's dark horse time.