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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Tenchusatsu who wrote (57120)	5/3/1999 8:16:00 PM
From: Scumbria	Read Replies (1) \| Respond to of 1572627

Ten, why wasn't this trick used in Pentium III? Almost all of the important control logic in the CPU core is tied in to the L1 cache access. It would probably be easier to start over again than to try to muck with that part of the pipeline. There are also the psychological aspects which make it very difficult to add raw latency to the cache. It goes against the the basic principles of data flow architecture which most CPU architects are trying to emulate. Scumbria