Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Altera -- Ignore unavailable to you. Want to Upgrade?

To: cecil who wrote (2038)	5/4/1999 6:29:00 PM
From: schlep	Read Replies (1) \| Respond to of 2389

Cecil, In time I will be glad to share more information. Currently I have preliminay information. I have looked at 20k400 delays, quite impressive across large blocks and interconnect distances. Regarding your V300 vs. 10k100 comparison. One needs to recognize that the M1.x compiler for Virtex has advantages and slightly different strategies for use when doing a Virtex design than when using Maxplus2 for Flex 10kA/E. Your 10k100 12 hour compile, I suspect used the timing driven synthesis in max2. While, this is the ideal methodology, it is not the best way to use the Max2 tool for best performance / compile time results. If you want to run a first pass overnight, go-ahead and use TDC for the first pass. Then back annotate to Rows and fix the 'straglers' in failed timing paths which were poorly placed. My experience has been 10-15 minute compiles with this method in 10k100 and 15-20 minutes in 10k200E (Pentium 400 Xeon with 512Mbytes). This would double with TDC to get better row timing. Don't forget to float pin assignments you just locked down if no board layed out yet. Quartus is showing decent results in its early stages. It would be unfair to compare it today with M1.x which is about 2 years more mature. I don't want to begin any debates. You asked for some indication which is why i share this with you. All i can say is that my experience has been for example with 10kE-1's with lots of manual constraints, i am able to pretty much rival Virtex -5 and -6 expertly manipulated as well. So far, unconstrained, Apex 20k400-1 is showing almost similar performance as the manually constrained 10kE-1. More importantly and impressive, it appears to enable this level of performance over very large blocks of logic compared to the 10kE and Virtex due to the new architecture. This does imply performance upside as one constrains these same paths as well as ease in obtaining higher performing circuits. I am sure your technical support people will be able to shed more light on this pretty soon. FWIW. schlep