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To: John Graybill who wrote (45616)	5/5/1999 4:16:00 PM
From: DJBEINO	Read Replies (2) \| Respond to of 53903

0.15µ technology dropped from semiconductor industry roadmap By Jack Robertson Electronic Buyers' News (05/05/99, 04:09:37 PM EDT) The updated version of the International Technology Roadmap for Semiconductors from the Semiconductor Industry Association (SIA) and SEMATECH released today confirms earlier EBN reports that the 0.15-micron chip generation has been dropped from the roadmap The long-delayed 1998 revision, which includes inputs from global chip makers, was released online at: www.itrs.net/ntrs/publntrs.nsf. By dropping the 0.15-micron chip generation, all other generations have been moved up one year. That now puts the 0.13-micron generation in 2002, the 0.10 generation in 2005 and 0.07-micron generation in 2008. By 2014, ITRS roadmap calls for a 1-terabit DRAM using 0.035-micron processing to be developed. Each generation of DRAM has been similarly advanced by one year. The first 1-gigabit DRAM samples are slated to be developed, according to the roadmap, by the end of 1999, and 4-Gbit samples by 2002. Then 16-Gbit DRAMs would initially be developed by 2005 and 64-Gbit by 2008. The new roadmap extended the chip timetable to the year 2014 for the first time. It calls for 0.035 micron node feature size or 0.025-micron isolated lines. That would allow fabrication of 1-terabit DRAMs. Microprocesors at these design rules would have 390 million logic transistors/cm2. The roadmap also updated projections for the calculation of cost/bit for DRAMs, dropping to 40-microcents in 1999 from 60-microcents, which was projected for this year in earlier roadmap versions. The new roadmap also dropped the “cents-per-pin” package cost for semiconductors this year to 70 cents-$2.52 range from earlier versions with a $1.25-$2.80 packaging cost range. In 2002, the packaging cost is now estimated at 60-cents-$2.16 compared to previous estimates of $1.15-$2.30. Part of the packaging cost reduction is due to scaled-down projections of I/O connections. The new roadmap estimates that in 1999 the number of chip-to-package pads for high performance microprocessors will be 1867, compared with 2000 projected earlier. For value-priced MPUs, the number of chip-to-package pads this year drops to 934 from 975. ebnews.com