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To: Zeev Hed who wrote (19868)5/10/1999 7:51:00 PM
From: MileHigh  Respond to of 93625
 
Monday May 10, 8:30 am Eastern Time
Note: there is a subsequent correction for this article.

Company Press Release
SOURCE: LSI Logic Corporation

LSI Logic Now Offers 66-MHz FlexCore PCI Architecture In G11 (.25-Micron) Process
With Three Interface Options and Pre-Verified Timing, the PCI FlexCore Architecture Enhances LSI Logic's Leadership in High Speed I/O

MILPITAS, Calif., May 10 /PRNewswire/ -- LSI Logic (NYSE: LSI - news), The System on a Chip Company®, announced today that it is now offering its 66-MHz FlexCore® peripheral components interconnect (PCI) architecture in G11(TM) (0.25-micron) process technology. The PCI-66 core, initially introduced in March 1997 in the G10® (0.35-micron) process technology, is the industry's first 66-MHz modular hard macro implementation of the PCI interface. This core is capable of supporting bus speeds of up to 66-MHz with bus widths of either 64- or 32-bits. This core enables designers to develop high performance systems on a chip providing up to 528-Mbytes/second of peak bandwidth.

The PCI-66 core is part of LSI Logic's extensive CoreWare® library for system-on-a-chip designs. It is developed for integration into an ASIC and provides complete interface solutions for the PCI bus, enabling the development of highly integrated PCI adapter cards and host-bridge ASICs. The PCI-66 core can be used with LSI Logic's other leading-edge I/O products such as the Rambus D-RAC core, the GigaBlaze® core, and the HyperPHY(TM) core for a high-performance, system on a chip solution.

''We decided to use the PCI-66 FlexCore architecture because it accelerates our time to market, it is easily integrated, completely verified, and fully supported,'' said Ottawa, Ontario-based Bill Swift, director of engineering for Cisco's Optical Internetworking Business Unit. ''LSI Logic is a recognized leader in high-speed I/O with a strong track record in core integration. They were the obvious choice for providing the PCI core.''

As a hard macro, with a fixed layout, the PCI-66 core has precise clocking and pre-verified timing for operation up to 66 MHz in 32- or 64-bit modes. This solution lets the ASIC designer focus on value-added logic and ASIC integration rather than solving the timing challenges of the PCI interface. Soft macro PCI cores, on the other hand, can require a significant effort to reach timing closure. In addition, the PCI-66 FlexCore architecture has been extensively tested with over 40 million cumulative simulation cycles. The architecture has also been proven in both test chip silicon and used in production ASICs.

The modular FlexCore architecture provides the flexibility required for easy use by offering three interface options: (1) slave interface for PCI target applications, (2) master/slave interface supporting PCI host applications, and (3) master/slave/FIFO interface for full functionality with an asynchronous FIFO interface. These three interface options result in a flexible solution that lets the ASIC designer select the optimal configuration based on performance and cost requirements.

''Bandwidth demands on the PCI bus have increased from a number of areas, including performance-intensive embedded applications such as multi-function peripherals, storage subsystems and communications subsystems. Coupled with the need for higher densities, higher performance, and lower power, the PCI-66 in the G11 process is an ideal solution for many of today's high-speed I/O applications,'' said Rich Hovey, product line manager, Computer Products Division, LSI Logic.

The LSI Logic CoreWare methodology program provides a full range of complex building blocks, proven design methodology, leading edge technology and applications support necessary to build a complete system on a chip uniquely optimized for the target application. The CoreWare library includes a full range of RISC® microprocessors, Rambusa D-RAC, Fibre Channel, GigaBlaze, ATM, USB, Ethernet-10, and PHY-110 cores.

About LSI Logic

LSI Logic, The System on a Chip Company®, is a leading supplier of custom high-performance semiconductors, with operations worldwide. The company enables customers to build complete systems on a single chip with its CoreWarea design program, which increases performance, lowers system costs and accelerates time to market. LSI Logic develops application-optimized products in partnership with trendsetting customers, and operates leading-edge manufacturing facilities to produce submicron geometry chips. The company maintains a high level of quality as demonstrated by its ISO 9000 certifications. LSI Logic Corporation is headquartered at 1551 McCarthy Boulevard, Milpitas, California 95035, lsilogic.com.

NOTE: The LSI Logic logo design, GigaBlaze, FlexCore, G10, The System on a Chip Company and CoreWare are registered trademarks and G11, and HyperPHY are trademarks of LSI Logic Corporation. All other brand or product names may be trademarks or registered trademarks of their respective companies.

SOURCE: LSI Logic Corporation

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To: Zeev Hed who wrote (19868)5/10/1999 7:54:00 PM
From: MileHigh  Respond to of 93625
 
Monday May 10, 11:48 am Eastern Time
Company Press Release
Denali Introduces Breakthrough Memory Model for Rambus Applications
Denali's Turbo Channel Model for Rambus Subsystem Design is Shipping Now
PALO ALTO, Calif.--(BUSINESS WIRE)--May 10, 1999--EDA company and memory modeling and verification specialist, Denali Software, Inc., announced today that it is shipping its Turbo Channel model, a simulation model for the Rambus Channel. Compaq Computer Corporation (NYSE: CPQ - news) is among the first systems houses to use it in the development of next generation Alpha processors. (See related press release today).

The new product models the Rambus Channel rather than an individual memory component. For ASIC memory controller designers, it preserves accuracy and speeds up systems simulation as much as 20 times.

According to Sanjay K. Srivastava, president of Denali Software, ''RDRAM has a new packet-based protocol. We created new technology for Rambus memory system design so that the design of Rambus applications would be faster and offer better memory system debugging capabilities. We believe that our Turbo Channel model dramatically reduces the barrier to creating memory controllers with the Rambus memory interface. This belief is validated by the rapid pace at which our technology is being adopted by leading systems houses.''

What Others Are Saying:

According to Dataquest, RDRAM production is estimated to account for 5 percent of the DRAM megabytes shipped in 1999, growing to approximately 31 percent in 2000. Already, 13 of the top memory manufacturers supplying over 96% of the world market have signed license agreements to produce RDRAM devices.

Kevin Donnelly, vice president of the Physical Architecture Division at Rambus Inc., noted, ''We continue to be pleased with Denali's commitment to our Rambus technology and believe tools like Denali's are critical to Rambus-based memory system design.''

What's New-technology and performance:

Denali's Turbo Channel model implements patent-pending techniques for performance optimization when the Rambus Channel being modeled has many components connected to the channel. The implementation does not sacrifice any accuracy. In most of the cases, the simulation performance shows n times improvement where n is the number of RDRAM components on the Rambus Channel being simulated. The performance numbers are measured against single instance models.

More About Denali's and Rambus Modeling:

Denali's Turbo Channel model implements modeling technology to improve design and verification of Rambus-based memory controllers and systems. This new product expands Denali's Rambus product line by adding improved Rambus support. It is an option to Denali's RDRAM verification kit (announced in October 1998).

Denali's models are compatible with popular HDL development environments and fully integrated with popular verification tools, including hardware/software co-verification, cycle-based simulation and automatic test bench generation tools.

Written in C, with an open C language API, systems and ASIC designers can easily add custom debug or visualization tools to Denali's memory simulation models.

Pricing and Availability:

Denali's Turbo Channel model is shipping now. The model is $5000 (USD). Denali's RDRAM Verification kit with the Turbo Channel model and Denali's AutoTest(TM) automatic test vector generation program and debugging software is $8000 (USD). Denali models and tools run on Solaris, SunOS, Windows NT/95, HPUX, Compaq Tru64 UNIX, IRIX and AIX operating systems.

About Denali Software:

Denali Software was founded in 1994 to increase designer productivity by providing complete memory modeling solutions. Its Memory Modeler(TM) allows designers to instantly create simulation models for the latest memory components and sub-systems. Denali works closely with leading EDA vendors to ensure the compatibility and interoperability of its memory simulation and verification tools. The company is a member of Cadence Design Systems' (NYSE: CDN - news) Connections, Mentor Graphics' (NASDAQ: MENT - news) OpenDoor, and of Synopsys' (NASDAQ: SNPS - news) Tap-in programs.

Denali Software, Inc. is located at 644 Emerson Street, Suite 7, Palo Alto, CA, 94301 USA. 650 325-7241, FAX: 650 325-5724, www.denalisoft.com.

Notes to editors:

A graphic showing Denali's Rambus Channel model simulation time comparisons is available on request.

Acronyms and definitions: API: Application Programming Interface ASIC: Application Specific IC DRAM: Dynamic Random Access Memory EDA: Electronic Design Automation HDL: Hardware Description Language IC: Integrated Circuit

Rambus: Memory technology developed and licensed by Rambus Inc. RDRAM: Rambus Dynamic Random Access Memory device. This component can transfers up to 1.6 billion bytes per second.

Rambus system: The memory subsystem consists of a processor or controller with the Rambus interface, the bus (Channel) supporting one or more RDRAM devices and the RDRAM devices and the bus connecting of one or more RDRAM devices. Info from whatis.com

SoC: System-on-a-Chip SOMA: Specification of Memory Architecture

Reader Service Contact:

Denali Software, Inc., 644 Emerson St., Suite 7, Palo Alto, CA, 94301USA. 650 325-7241 x18, FAX: 650 325-5724, www.denalisoft.com, Alissa Gogolewski, alissa@denalisoft.com.

Tru64 UNIX is a trademark of Compaq Computer Corporation. UNIX is a registered trademark in the United States and other countries licensed exclusively through X/Open Company Ltd.

Rambus and RDRAM are registered trademarks of Rambus Inc. Direct Rambus and Direct RDRAM are trademarks of Rambus Inc. AutoTest and Memory Modeler are trademarks of Denali Software.

Denali Software acknowledges trademarks or registered trademarks of other organizations for their respective products and services.

--------------------------------------------------------------------------------
Contact:

ValleyPR
Georgia Marszalek, 650/345-7477
georgia@valleypr.com



To: Zeev Hed who wrote (19868)5/10/1999 7:56:00 PM
From: MileHigh  Respond to of 93625
 
Monday May 10, 11:43 am Eastern Time
Company Press Release

Denali Software Tools Used in the Development of Next Generation Alpha Processors

Compaq selects Denali for Rambus subsystem design

PALO ALTO, Calif.--(BUSINESS WIRE)--May 10, 1999--EDA company and memory modeling and verification specialist, Denali Software, Inc., announced today that Denali Software and Compaq Computer Corporation (NYSE:CPQ - news) have concluded an agreement for Compaq to use Denali's memory system design tools in the development of next generation Alpha microprocessors.

The design tools covered by the agreement include Denali's new Turbo Channel simulation model, a Rambus DRAM (RDRAM) memory modeler and verification kit for electronic systems memory design. (See related product announcement today.)

Compaq licensed the Turbo Channel model from Denali for verification of its next generation Alpha microprocessor. Compaq will integrate the model into its Alpha behavioral simulation environment, capable of running multiple, large-scale multiprocessing simulations. Denali's Turbo Channel model runs on Compaq's high performance 64-bit Alpha systems.

Scott Gordon, Compaq's Director of Foundry and Alliance Programs (Shrewsbury, MA), said, ''By combining Denali's fast Turbo Channel modeling technology with our high performance Alpha Tru64 UNIX servers, we are able to achieve the simulation performance that our design team needs, while benefiting from a standard model used across multiple RDRAM memory system designs in the industry.''

''It is partnerships with leading edge design teams like those at Compaq that have helped helps us continuously improve the performance of our memory design solutions,'' noted Sanjay K. Srivastava, President of Denali Software. ''Working with Compaq gave us the opportunity to evaluate the superior performance of Compaq's 64-bit Alpha platform.''

About Denali Software

Denali Software was founded in 1994 to increase designer productivity by providing complete memory modeling solutions. Its Memory Modeler(TM) allows electronic systems designers to instantly create simulation models for the latest memory components and sub-systems. Denali works closely with leading EDA vendors to ensure the compatibility and interoperability of its memory simulation and verification tools. The company is a member of Cadence Design Systems' (NYSE: CDN - news) Connections, Mentor Graphics' (NASDAQ: MENT - news) OpenDoor, and of Synopsys' (NASDAQ: SNPS - news) Tap-in programs. Denali Software is located at 644 Emerson Street, Suite 7, Palo Alto, CA, 94301 USA. 650 325-7241, FAX: 650 325-5724, www.denalisoft.com.

Contact information for quote Scott Gordon, Compaq, 508-841-3286, scott.a.gordon@compaq.com

Acronyms and definitions: DRAM: Dynamic Random Access Memory EDA: Electronic Design Automation Rambus: Memory technology developed and licensed by Rambus

Corporation RDRAM: Rambus Dynamic Random Access Memory is a memory

subsystem that promises to transfer up to 1.6

billion bytes per second. The subsystem consists of

the RAM, the RAM controller, and the bus (path)

connecting RAM to the microprocessor and devices in

the computer that use it.

Info from whatis.com

Rambus, RDRAM and the Rambus logo are registered trademarks of Rambus Inc. Direct Rambus, Direct RDRAM are trademarks of Rambus Inc. Memory Modeler is a trademark of Denali Software. Denali Software acknowledges trademarks or registered trademarks of other organizations for their respective products and services.

Reader Service Contact: Denali Software, Inc., 644 Emerson St., Suite 7, Palo Alto, CA, 94301USA. 650 325-7241 x18, FAX: 650 325-5724, www.denalisoft.com, Alissa Gogolewski, alissa@denalisoft.com.

--------------------------------------------------------------------------------
Contact:

ValleyPR
Georgia Marszalek, 650/345-7477
georgia@valleypr.com
www.denalisoft.com