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To: Shumway who wrote (19888)5/11/1999 5:31:00 AM
From: unclewest  Respond to of 93625
 
don't believe this has been posted yet...

Date: 05/06 16:42 EST

Solving the Memory Bottleneck in Your Computer; Texas Instruments Presents Paper on Burn-in Testing Memory Chips at IPC Chip Scale and Ball Grid Array National Symposium

SANTA CLARA, CALIF. (May 6) BUSINESS WIRE -May 6, 1999--A faster
desktop computer means little when a memory bottleneck can slow
everything down. Even casual computer users can suffer agonizingly slow
speeds, all because the memory isn't as fast as the processor inside.

One solution to the bottleneck is to improve the protocol, or
"handshake," between the memory and processor chips. Since the average
computer can handle anywhere from 200 million to 500 million handshakes
per second (also known as megahertz), the protocol is a critical
component to overall processing.

That's why the high-tech industry is looking hard at new memory
management technologies: to bring memory chip speeds up to the fastest
processors for better computing. The stakes are high because memory
chips such as DRAMs, SRAMs, and flash memory are used in a wide range
of computers, office equipment, gaming systems and a growing group of
information appliances.

"Today's microprocessors are outpacing the available memory bandwidth
and creating a desperate 'need for speed' in memory chips," said James
A. Forster, Ph.D., engineering manager in Texas Instruments'
Interconnection Business who is presenting a paper at the IPC Chip
Scale and Ball Grid Array National Symposium. His paper on "Rambus(r)
-- Challenging Burn-in Socket Design to Accommodate Differing CSP
Outlines," describes the issues facing designers of testing sockets who
must address the faster speeds of memory chips that use the Rambus
protocol and chip-scale package design.

"The continued consumer demand for smaller and more capable computers
and electronic devices is driving the need for faster memory," Forster
said. "To satisfy this need manufacturers have opted to add new memory
management protocols, such as Rambus, while using much of the
established package and assembly manufacturing process and
infrastructure. One challenge that remains is how to functionally test
these faster memory chips to ensure quality."

IPC Chip Scale and Ball Grid Array National Symposium is hosted by the
Institute for Interconnecting and Packaging Electronic Circuits (IPC)
and features new and emerging technologies and business trends for the
electronic interconnection industry.

A copy of Dr. Forster's presentation is available by contacting Lynda
Armstrong of Texas Instruments' Interconnection Business at (508)
236-5388.





To: Shumway who wrote (19888)5/11/1999 5:45:00 AM
From: unclewest  Read Replies (1) | Respond to of 93625
 
great little rmbs story here. doesn't copy, you have to go to the site.

click link
scroll down to "rambus dues"
click full story

electronicnews.com



To: Shumway who wrote (19888)5/11/1999 10:37:00 AM
From: MileHigh  Respond to of 93625
 
Shumway,

I thought the Toshiba news was positive and further validation of the ramp up actually occurring, was that your take as well?

MH