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To: KM who wrote (30213)	5/17/1999 9:22:00 AM
From: Duker	Respond to of 70976

TSMC launches 0.18-micron process, plans steep ramp in volume fabs A service of Semiconductor Business News, CMP Media Inc. Story posted 6 a.m. EST/3 a.m., PST, 5/17/99 HSINCHU, Taiwan -- Silicon foundry supplier Taiwan Semiconductor Manufacturing Co. Ltd. here today officially announced availability of its 0.18-micron CMOS process technology and said it will make available a copper option for the top two layers of metal interconnect in the third quarter this year. For the past year, TSMC has been developing a 0.18-micron (drawn) process, called CL018, which features six metal layers of interconnect with a low-k dielectric insulator made of fluorinated silicon glass (FSG). Late last year, TSMC began producing test chips and prototypes using the technology, and today the world's largest foundry company said it has begun shipping 0.18-micron products to customers. TSMC now plans to add enough 0.18-micron capacity to fabricate 34,000 eight-inch wafers in 1999 and over 600,000 wafers next year, said F.C. Tseng, president of TSMC. TSMC's aggressive push into the 0.18-micron process generation comes as major silicon foundries begin to close the gap between themselves and large integrated device manufacturers, such as IBM Corp. and Intel Corp. TSMC's nearby foundry rival, UMC Group, announced late last year that it had successfully produced prototype ICs with a new 0.18-micron (drawn) process. Both UMC and TSMC are planning to roll out copper processing for high-performance interconnects in the third quarter. TSMC expects to "receive six additional customer tape outs this quarter," said Tseng, "and we see over 30 more tape outs planned for the second half of 1999." The foundry giant also sees wafer-processing demands growing after last year's recession. To build up both its 0.18- and 0.25-micron capacity, TSMC has increased its 1999 capital spending for the joint-venture WaferTech fab in Camas, Wash., and to transfer the new 0.18-micron process technology to a couple of the company's volume production plants in Hsinchu. TSMC's new Fab 6 in Tainan, located in southern Taiwan, will begin receiving production equipment in the fourth quarter, and it is slated to begin processing 8-inch wafers by April 2000, company managers said. TSMC believes its new process is one of the few "true" 0.18-micron technologies to hit the market. "Our observation is that many of the previously announced technologies have been shrinks of 0.25-micron processes, where primarily the gate length was reduced," said Roger Fisher, vice president of marketing for TSMC, based in San Jose. He said TSMC has built its 0.18-micron process from the ground up to reduce the interconnect contact spacing in the technology's six-layers of metal. In fact, TSMC claims its metal pitch is the tightest among 0.18-micron processes. The first-level metal is 0.46 micron with the next four layers being 0.56 micron. The final sixth layer of metal is 0.90 micron. The fine metal pitch enables the process to produce 100,000 to 120,000 gates per mm². TSMC said its new process has also been developed to fabricate an SRAM cell size of 4.65 square microns--40% smaller than the cells produced by TSMC's 0.25-micron process. The new technology will process ICs that operate at over 400 MHz and on-chip memory speeds of over 500-MHz, according to TSMC. With a 0.18-V supply, the power gate dissipation of devices will be less than 30 nanowatts/MHz, the company said. After processing copper wafers in development for nearly one year, TSMC concluded that it is only feasible today to process ICs with copper on the two layers of interconnect in volume production. "The lower levels of metal have relatively short wire lengths, and in those cases the delays are dominated by capacitance," Fisher said. "In that case it makes more sense to take advantage of low-k material." To reduce the capacitance, TSMC is introducing FSG into production with its 0.18-micron process using aluminum wiring. The FSG insulator has a dielectric rating of between 3.3 and 3.4 compared to just above 4 with conventional silicon dioxide. "We are working towards a combined copper and low-k process that will be viable [for all layers of interconnect], and we expect to have that no later than the 0.13-micron generation," Fisher said. In the third quarter this year, TSMC plans to introduce a second-generation 0.18-micron process technology, which will shrink the drawn gate lengths to 0.13 micron for 1.5-V operation of core functions and higher device speeds. --------------------------------------------------------------------------------