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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Scumbria who wrote (58428)	5/17/1999 3:19:00 PM
From: Charles R	Read Replies (3) \| Respond to of 1574890

CPU biz enthusiasts, Dan Niles has come up with a research note that highlights some info that could be of interest to this thread: - AMD is yielding K7 over 600MHz and most of the K6s over 400 - K7 launch set for late June - Cyrix is dumping product in the market (clerence sale) - AMD sitting on 1 Mu inventory - Intel dropping ASPs to ensure AMD does not get the sockets it lost during manufacturing problems last week (turning out to be expensive for Intel) - Celeron OEM prices significantly below list - Intel market segmentation breaking down fast (i.e. more Celerons in business and consequently lower ASPs) - Intel 0.25 ramp fantastic and cost reduction well above plan and possibly 2Q ahead of AMD - Intel expected to do another price cut in June to counter K7 Suggests people run out of the PC CPU and OEM market segment on good news - such as good results from DELL and HP. What do you guys think? Chuck

To: Scumbria who wrote (58428)	5/17/1999 9:26:00 PM
From: grok	Respond to of 1574890

Re <So Digital goes with an oversized multi-cycle L1 cache for the 21264. Yet even with a lengthened L1 access time, it's still 18% slower in clock speed than the 21164. Of course, the performance is much better even at the slower clock speeds, but it goes against Scumbria's argument that a multi-cycle L1 cache is the key to higher clock speeds.> What everyone is missing from this argument is that the 21264, while allowing 2 cycles for dcache access, actually accesses the dcache TWICE during these two cycles. This is their way of doing a dual-access cache. If you want evidence check the 1997 ISSCC Digest page 176 which reads "The cache supports either two 8B reads to arbitary addresses per CPU cycle by phase pipelining the word and bit-lines or one (up to 16B) combined victim extract and write to a single address." Also checkout the spice waveforms shown on page 135 of the Slide Supplements which shows how the two accesses follow each other through the cache. Pretty hairy stuff! Through this phase pipeling they can sustain two accesses every cycle. So it is not so obvious if this cache can run at a higher frequency than a conventional single cycle cache. Of course it would give high performance at the same freq due to the dual access.