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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: grok who wrote (58503)5/17/1999 9:04:00 PM
From: Scumbria  Respond to of 1575396
 
KZ,

I don't have any pointers but I looked up the 1995 ISSCC Digest which has 21164 on page 182 where it reads "the data cache ... has a one-cycle access for both reads and writes."

Interesting. I wonder if they are fudging about their definition of 1-cycle cache access. Normally the TLB translation and cache access are included together.

I don't believe that it is possible to do both at 700 MHz in a 0.35u process- even for the small cache.

Scumbria



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