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To: Lewis M. Carroll who wrote (2049)	5/18/1999 10:29:00 PM
From: schlep	Respond to of 2389

Lewis, Here is some sketchy information I have off the top of my head. I don know that your local FAE could show you some Powerpoint slides covering all of these questions. Here is my brief shot at some answers: You EE types seen SignalTap? Looks pretty neat but I missed a couple of things... 1. How much room should you reserve for the instantiation of the SignalTap block? A: Signal Tap mostly relies on the ESB (ram blocks) which are 2kbits each. The number of blocks you need depend on the number of signals and depth of each trace. Example 32 ESBs would provide enough data storage for 2kx32bits! Only a couple of hundred lcells needed of support logic for such a function. Both the 32 ESBs and couple hundred lcells are faily insignificant in the 20k400 (104 ESB and 16k lcells) 2. Do you have to use JTAG or can you packetize the data to ship out over an alternate method (ethernet frames maybe?) A: Currently, ALTR sells the MASTER_BLASTER for hard interfacing (not sure if jtag). However, since the signal tap is a macrofunction, it would be reasonable that you could design in your own interface to send data out any protocol you desire. 3. Assuming you start your design including the SignalTap megafunction, how much re-compilation (if any) is necessary if you change the signals you want to watch? A: When the Quartus Incremental recompile is implemented, only changed pieces of your design would need to be re-compiled. The incremental recompile decision algorithms are quite sophisticated. 4. Does the megafunction slow the rest of the 20K device it's in down at all? A: Doesn't slow down the rest of the system at all - pretty nifty. The SignalTap function will be pipelined automatically for the simple condition / trigger logic. 5. Does Xilinx have anything like this in the works? Might be patented by ALTR. Many designers find Signal Tap one of the most desirable features in Quartus. -schlep PS- As an EE I feel obligated to share this info with you but would really prefer to have you solicit this from you local ALTR fae. Also, the comp.arch.fpga new group is sometimes another good source. (from their Dallas office) amandan@altera.com brianj@altera.com