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Technology Stocks : C-Cube -- Ignore unavailable to you. Want to Upgrade?

To: VidiVici who wrote (41475)	5/24/1999 6:24:00 PM
From: Black-Scholes	Respond to of 50808

My rumor mill is tapped out. All indicators pointed to a buyout last Monday. Didn't happen. But checkout the option activity today for June 30's and 35's. Someone thinks something is going on.

To: VidiVici who wrote (41475)	5/24/1999 6:27:00 PM
From: Black-Scholes	Respond to of 50808

Speaking of rumors, what happen to the TV part company in Norway. Maybe that was a big hoax. I thought it was just obscure enough to be true.

To: VidiVici who wrote (41475)	5/25/1999 1:45:00 PM
From: DiViT	Read Replies (1) \| Respond to of 50808

Verplex's New Transistor Extraction Tool Speeds Verification And Simplifies Intellectual Property Reuse Of Custom Designs 05/24/1999 Business Wire (Copyright (c) 1999, Business Wire) SAN JOSE, Calif.--(BUSINESS WIRE)--May 24, 1999--Verplex Systems, Inc. announces the release of Tuxedo-LTX(TM), a leading-edge transistor extraction tool which automatically produces Verilog simulation models from digital transistor-level netlists. The tool serves a variety of critical verification needs for the growing number of customers embracing transistor-level design for timing-critical blocks. Tuxedo-LTX is now available in the marketplace and has been used successfully by companies pushing the performance limits, such as C-Cube Microsystems, Chameleon Systems and VIA Technologies. Transistor Extraction Tuxedo-LTX accepts a switch-level Verilog or SPICE transistor netlist as input and automatically extracts a higher level Verilog description from it. It does so by analyzing the connectivity of the transistors and assigning Boolean functions to each of the nodes based upon a rigorous analysis of the circuit. The tool then expresses the Boolean functions of the output nodes as a functional Verilog description. A highly versatile tool, Tuxedo-LTX is useful for simulation acceleration, emulation, automatic test pattern generation (ATPG), automatic library generation, re-targeting, design reuse and reverse engineering. Combined with Verplex's Tuxedo-LEC equivalence checker, it becomes a powerful verification tool for full custom designs. Adjunct to Layout vs. Schematic (LVS) Designers use LVS to verify that full custom layouts are correct with respect to their schematic representations. LVS, however, does not verify that the Verilog simulation models representing the schematics are correct. Until now, designers have relied upon slow and incomplete SPICE or switch-level Verilog simulations for this purpose. In contrast, the combination of Tuxedo-LTX and Tuxedo-LEC exhaustively verifies Verilog simulation models against transistor netlists without using test vectors. Michael Howard, Design Verification Manager of C-Cube Microsystems Inc., stated, "Portions of our designs run at very high speed and are mathematically complex, so our chips require the use of full custom, transistor level circuitry along with our synthesized blocks. Tuxedo-LTX is the only product we have seen that truly enables us to equivalence check our entire design, from RTL through mixed gate and transistor level netlists. Tuxedo-LEC handles arithmetically complex logic that bogs down other tools or stops them entirely. The tight integration of Tuxedo-LTX and Tuxedo-LEC simplifies the task of verifying our complex, mixed gate and transistor level designs by providing a smooth flow and common debug interface." Additional Uses Tuxedo-LTX is particularly useful in simulation-based verification methodologies. Extracted Verilog simulates far faster than SPICE simulation or switch-level Verilog. As an input to an emulator, extracted Verilog verifies transistor-level blocks as part of an integrated system, including software. As an input to ATPG tools, it provides the internal functional information needed in order to generate test vectors. Howard stated, "Tuxedo-LTX automatically and accurately produces models we use for ATPG. Without it, we would have to produce these models manually, which is both time consuming and error prone." Tuxedo-LTX also greatly assists in the reuse of intellectual property and legacy designs. Extracted Verilog from cores and library cells automates the traditionally tedious and error-prone process of creating simulation models for them. By applying the extracted Verilog as input to a logic synthesis tool, older transistor-level blocks are retargeted into standard ASICS. Analyzing the extracted Verilog simplifies the process of reverse engineering transistor-level designs of unknown functionality. Flexible, Friendly Architecture Tuxedo-LTX handles NMOS or PMOS designs containing pre-charged, pass-gate tri-state or domino logic. MOS direction and design hierarchy flattening can be determined automatically or can be manually controlled by the user. Tuxedo-LTX automatically extracts sequential elements, such as flip-flops or latches. The tool provides pattern matching for full custom circuits that are not strictly digital in nature, and thus may be difficult to automatically recognize. Tuxedo-LTX includes a hierarchical browser to guide the extraction process and a graphical schematic viewing environment to aid in design visualization. It is completely integrated with Verplex's Tuxedo-LDD diagnosis environment to speed the debugging of mismatches. Tuxedo-LTX is now shipping for Solaris and HP-UX platforms and is priced at $95K per floating license. Verplex Systems, Inc. Verplex Systems, Inc., founded in June 1997, develops, markets and supports formal verification solutions for complex system-on-a-chip ICs. Verplex is aggressively developing advanced technologies and its mission is to become the superior technology provider for the formal verification market. Verplex targets ASIC and IC engineers that need to increase their overall design and verification productivity. For more information, visit www.verplex.com. Note to Editors: Verplex, Tuxedo-LEC and Tuxedo-LTX are trademarks of Verplex Systems, Inc. Contact: CONTACT: Verplex Systems, Inc. Dino Caporossi, 301/390-2718 dino@verplex.com or Paula E. Jones Consulting Paula Jones, 650/967-3711 paula@bizblues.com 11:01 EDT MAY 24, 1999