Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: grok who wrote (59931)	5/28/1999 1:43:00 PM
From: Scumbria	Read Replies (1) \| Respond to of 1574001

KZ, The thing is that today's micros only usefully dispatch and retire about 1 instruction per cycle. So getting this up to 2 would represent a massive breakthrough. The average is 1 per cycle retirement. If dispatch was limited to 1 per cycle, the average would go down. The problem that academic CPU types have had is that they tend to focus on the instruction sequencer, and ignore the overwhelming impact of the DRAM subsystem. How many dataflow architects have been sorely disappointed by the 1.0 IPC when the silicon came back? Scumbria