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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Scumbria who wrote (59979)	5/29/1999 4:06:00 PM
From: grok	Read Replies (1) \| Respond to of 1574333

Re: <There isn't any reason not to put a cache address simulator into the compiler. It is fairly simple and would allow the cache movement instructions to be automatically utilized.> Sounds cool. I'm not a sw expert. I do know that leading edge compiler work is being done by Wen-Mei Hwu at U of Illinois. This is from their web page: "Computer Architecture In the area of computer architectures, research is being performed on the design of highly pipelined microprocessors. Optimizing compilers are being investigated to make efficient use of registers and cache memories based on the actual run-time profiles of programs. In addition, new super scalar architectures that issue more than one instruction per machine cycle are being investigated." This is a very modest description of their work. Notice the part about "cache memories based on the actual run-time profiles of programs" which sounds like what you're talking about. I'll try to find some real meat about their work.

To: Scumbria who wrote (59979)	5/29/1999 4:28:00 PM
From: grok	Respond to of 1574333

Here is more on Wen-mei Hwu's work at UofI: "The objective of IMPACT (Illinois Microarchitecture Project utilizing Advanced Compiler Technology) is to provide critical research, architecture expertise, and compiler prototypes for the microprocessor industry. This objective is accomplished by analyzing and demonstrating the level of hardware and compiler support required by architectural enhancements in order to understand the cost and effectiveness of these enhancements. IMPACT's primary focus is on exposing, enhancing, and exploiting instruction-level parallelism (ILP)." I can assure you that Intel's IA-64 team knows Wen-mei very well.