SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Scumbria who wrote (60059)6/1/1999 2:50:00 AM
From: maroon  Read Replies (1) | Respond to of 1582259
 
And why couldn't anyone else do this. The only parameter the K7 can control is (address out) and (data hold). Does Intel have a problem with these parameters?



To: Scumbria who wrote (60059)6/1/1999 12:48:00 PM
From: Elmer  Read Replies (1) | Respond to of 1582259
 
Re: "The interface to SDRAM would have to be slowed down, but the L3 cache should be able to run at 200 MHz."

DEC showed a design that achieved the high system bus speeds using 83MHz SDRAMs. They just used multiple interleaved banks.

EP


HomeMailHotSubjectMarksPeopleMarksKeepersSettings
Terms Of UseContact UsCopyright/IP PolicyPrivacy PolicyAbout UsFAQAdvertise on SI
© 2026 Knight Sac Media.  Data provided by Twelve Data, Alpha Vantage, and CityFALCON News