Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: Elmer who wrote (82497)	6/2/1999 2:06:00 PM
From: grok	Read Replies (1) \| Respond to of 186894

RE: <It would seem that, because of the higher frequencies involved, the penalty for a page miss or row miss is less with RDRAM. You're only adding 2-3 clocks at 400MHz as opposed to 100MHz currently.> I think that there are some misconceptions here. The 400 MHz (with double data rate) does not decrease access time. You've still got the internal time inside the dram chips. Moving address into the dram and data out of it is similar btween sdram and drdram since sdram has lower frequency but uses more pins. For example, consider a chip with 128 bit data bus using eight 4Mbitx16 100 MHz sdram and another chip with one 400 MHz double edge data drdram port which uses 16 bits of data. To transfer a 32 byte cache line requires 2 clocks with sdram (20 ns) or 8 clocks with drdram (20 ns). So in this case they both take the same amount of time to transfer 32 bytes. Of course sdram takes a lot more pins.