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Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: Aaron Cooperband who wrote (82543)	6/3/1999 12:12:00 AM
From: Gerald Walls	Read Replies (1) \| Respond to of 186894

Why do they bother to print these chips around the edges, since they will obviously end up in the trash bin? Beats me. Also, it seems that if you shifted certain rows so that they were out of alignment with the rows above and below you could squeeze in a few extra chips. Why don't they do this? My guess is that the outer rim is very-low yield anyway and it's not worth the effort. It would seem to my layman's brain that if there were going to be imperfections in the silicon crystal they would be on the periphery. It could be that if you tried to squeeze chips out of these areas then you could actually end up with more chips touching the low-yield area and end up with fewer working chips. Or maybe I'm completely wrong.

To: Aaron Cooperband who wrote (82543)	6/3/1999 12:59:00 AM
From: Elmer	Read Replies (1) \| Respond to of 186894

Re: "In Intel's annual report there is a picture of a processed wafer. There are many partial chips on it all around the edges." The mask plates that produce the die actually contain more than 1 die on them. There may be 2 or 4 etc. That's why you see partial die around the edges. And rest assured that the die have positioned to produce the greatest number of complete die possible on a round wafer. Furthermore, numerous long term reliability studies have shown that die produced on the outside of a wafer tend to be more prone to early life failures. Some companies purposely scrap die from the outside of the wafer, even if they are complete and test out as fully functional. Too risky. EP

To: Aaron Cooperband who wrote (82543)	6/3/1999 1:18:00 PM
From: Paul Engel	Read Replies (1) \| Respond to of 186894

Aaron - Re: "Why do they bother to print these chips around the edges, since they will obviously end up in the trash bin? " In some cases, the master reticle will contain 2 (or more) images sites adjacent to each other. These are "printed" simultaneously, and at the edge one invariably falls partially "off" the wafer and the other "on" the wafer. A second reason could the x-y stepping of the lithography machine which "steps" along X rows by Y columns - in a rectangular matrix. Re: "Also, it seems that if you shifted certain rows so that they were out of alignment with the rows above and below you could squeeze in a few extra chips. Why don't they do this? " After wafer manufacturing, the individual die are "probed" and the wafer probe machines expect a regular x-y matrix of die locations. Moreover, in ASSEMBLY, the wafers are literally SAWN apart with a diamond-tipped saw blade, and again the stage runs in a regular X-Y matrix, so all the scribe lines - between die locations - have to run in perfect, CONTINUOUS, rectangular array of X-Y "lines". Or else the sawe blade will cut through actual die if the die sites are OFFSET. Paul