Here is an old (circa 1997?) article from our friends over at IBM on Cu ... I was actually testing out www.google.com (after the article in the WSJ) ... I thought the article was kind of decent, albeit a bit dated ... just a random article that isn't a bad read.
--Duker
Back to the Future: Copper Comes of Age
In Brief:
IBM's announcement on September 22 that it will soon start full-scale manufacture of chips that use copper, rather than aluminum, circuitry stemmed from decades of basic research and effective teamwork among individuals from the Research and Microelectronics divisions. Even in the lean years of the early '90s, copper's long-term strategic importance to the future of semiconductor technology guaranteed the necessary support to overcome the many problems blocking the way to a successful manufacturing process.
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Move Over Aluminum. Copper has arrived. Fulfilling a dream of several decades, IBM has introduced a technology that permits chip makers to use copper wires, rather than the traditional aluminum interconnects, to link transistors in chips. The advance gives IBM a significant lead in the race to create the next generation of semiconductors. "This is a major jump," says John Kelly, vice president for server development in IBM's Microelectronics Division. "It's been one of the holy grails of the industry. It was a matter of who could get there first."
The new copper interconnects will be implemented initially in IBM's seventh-generation CMOS (complementary metal-oxide-semiconductor) technology. The CMOS 7S process, as it is known, will show up first in high-end products, such as chips for mainframes and the PowerPC® chips used in IBM's RS/6000® and AS/400® computers. Eventually IBM expects to use CMOS 7S in all its systems. Similarly, copper itself will become more widespread in the semiconductor industry. "In time, everybody will be making copper chips," says John Heidenreich, manager of interconnect technology at the Thomas J. Watson Research Center, who has overseen work on copper since May 1994.
Heidenreich cites several compelling reasons for that projection. Copper wires conduct electricity with about 40 percent less resistance than aluminum. That translates into a speedup of as much as 15 percent in microprocessors that contain copper wires. Copper wires are also far less vulnerable than those made of aluminum to electromigration, the movement of individual atoms through a wire, caused by high electric currents, which creates voids and ultimately breaks the wires. As a remarkable added benefit, IBM's method of depositing copper wires on chips means a potential cost saving of up to 30 percent for the wiring or 10 to 15 percent for the full wafer. "Chip manufacturers will kill to save 3 percent," says Dan Edelstein, a research staff member at Watson who has taken a leading role in the copper project since October 1993. "A revolutionary advance in semiconductor technology like this that comes with no additional cost is unheard of in the industry."
Most important, the widths of copper wires can be squeezed down to the 0.2-micron range from the current 0.35-micron widths - a reduction far more difficult for aluminum. (A micron is over 100 times thinner than a human hair.) The copper-stimulated reduction in dimensions will permit designers to pack 150 million to 200 million transistors on a single chip. "As you get down to these very small dimensions, the conventional aluminum alloys can't conduct electricity well enough, or withstand the higher current densities needed to make these circuits switch faster," says Edelstein.
Not only does IBM's victory in the race put the company in pole position for manufacturing the next generation of semiconductors, but "it's going to force our competitors to spend development resources to catch up," says Heidenreich. "You can bet that every head of R&D at every semiconductor company is perusing this," says Drew Peck, an analyst at Cowen & Co., adding that even the most aggressive chip manufacturers are six to 12 months behind IBM in making copper technology practical.
Despite its many virtues, copper didn't become a success overnight. For, while the semiconductor industry recognized its potential more than 30 years ago, the perceived danger of using copper acted as a brake on its development as an interconnect. Not only does copper rapidly diffuse into silicon, the substrate in which the transistors are formed, but it changes the electrical properties of silicon in such a way as to prevent the transistors from functioning. "Copper was considered to be a killer to semiconductor devices," says IBM Fellow Lubomyr Romankiw. "The conventional wisdom was to stay as far away from copper as you could."
IBM's copper program managed to solve all the problems that faced the use of the element. One by one, scientists and engineers overcame the hurdles standing in the way of a viable technology. These ranged from a means of depositing copper on silicon to the development of an ultrathin barrier to isolate copper wires from silicon. The new technology is currently in the final stages of qualification at the Microelectronics Division's Advanced Semiconductor Technology Center (ASTC) in East Fishkill, New York. Full-scale manufacture will begin in 1998 at IBM's chip-manufacturing facility near Burlington, Vermont.
Teamwork, Persistence And Infrastructure
Three factors undergirded the effort that led to this new manufacturing technology: teamwork, persistence and research infrastructure. Without them, IBM would not have become the first company to solve all the problems that kept copper from becoming a viable, cheaper and scalable alternative to aluminum.
In 1991, recalls Barbara Luther, an interconnect manager in the project who is now on the rapid commercialization team at IBM headquarters, "we combined three groups working on copper technology into one team." Since then, individuals from Watson and the Microelectronics Division's Burlington and East Fishkill sites have collaborated to perfect the technology and prove its reliability and manufacturability. One notable paper on copper interconnects, published in 1993, contained the names of 33 co-authors from the two divisions. "We were one group," says Jill Slattery, a development manager at the Microelectronics Division who has overseen the program since 1994. "There weren't distinctions. It's really been a three-site consortium." The fruits of this combined effort appear in a seminal paper on the CMOS 7S technology that IBM presented at the Institute of Electrical and Electronic Engineers' IEDM conference in December 1997.
The team had to cope with more than the usual stresses of developing a revolutionary technology. In the early years of the effort, IBM's corporate fortunes were in serious decline; many duplicate efforts or projects not seen to be critical for the company's survival were scaled back or terminated. At the same time, the company decided to switch to CMOS technology (see Research, Number 3/4, 1995) and discontinued the bipolar technology program for which copper wiring was originally intended. Although copper benefits both technologies, the need was greater for the performance-driven bipolar chips, which had already reached the limits imposed by the higher-resistance aluminum wiring. ,
"That drastically lowered the priority of the copper program," says Watson's Jurij Paraszczak, a manager in the project. "You could see it dying as the resources were diverted to the higher-priority work of making the fastest CMOS possible for microprocessors." But the small group still involved with copper kept the faith, and sped up their development work. "The program survived because people were obsessed with having it work. We did everything we could to keep it going," recalls Paraszczak. "We knew that if we didn't make enough progress we might lose the whole technology," adds Luther.
As work continued, it became clear that copper offered significant advantages to CMOS technology and could be tailored for that application. That led to a crucial meeting. Helped by Paul Horn, now senior vice president of Research, the copper team presented to John Kelly its vision of the technology's future. As a result, Kelly was able to make the case that copper was a strategic technology that the company should not renounce under any circumstances. "We knew we were going to use copper," Kelly recalls. "It was a matter of when, not if. I basically told them to put their heads down and keep going."
Throughout, the project benefited from a broad range of Research skills that were brought to bear on specific challenges as they arose. "It's one of the hallmarks of research that you don't give up studying the basic science that underlies the issues," says Randy Isaac, vice president of systems, technology and science at Watson. "We were able to address a lot of problems because of the expertise in materials science we had in Research, developed over decades."
Roots Of The Technology
That expertise dates back to the late 1960s at Watson, when Romankiw succeeded in electroplating narrow wires of copper onto thin film heads for storage, using a masking method that deposited the copper only in circuit patterns where it was needed. Next, his team devised a means of depositing a complex copper structure on polyimide, a compound used as an electrical insulator in silicon chips. The industry reacted coolly to this advance. As Romankiw remembers it, "the reaction was: 'Very interesting, but why do we need it? Aluminum will carry us for a long time.' We were very premature."
That attitude began to change when it was realized that aluminum's vulnerability to electromigration would limit its use in ultra-small chip circuits with very high current densities. Ironically, the discovery by IBM scientists of a solution to the problem involved adding a small amount of copper to the aluminum. The alloy proved more resistant to electromigration than pure aluminum, and had chemical bonds strong enough to prevent copper atoms from diffusing into the surrounding silicon. So in its initial use, copper merely extended the useful life of aluminum.
As chips continued to decrease in size, however, it became clear that pure copper circuits had undeniable advantages that aluminum could not match. Making the element both practical and manufacturable demanded solutions to three major problems, explains Isaac: how to deposit copper; how to put in diffusion/adhesion barriers to prevent poisoning of the silicon; and how to pattern it. In fact, C.K. Hu and other scientists at Watson already had experience in copper deposition for packaging chips. Now, they sought a technique that would deposit very thin, even layers of copper both horizontally and in the vertical "vias" that link different layers of metal. That search had a surprise ending. The simplest approach was thought to be chemical vapor deposition (CVD), which involved deposition of solid copper from a gas. In case that didn't work, electrochemical researchers headed by Romankiw examined two other possibilities. The first, electroless plating, exposes a wafer to a chemical "reducing agent" in an electrochemical "bath" containing copper ions; the agent releases copper ions from the compounds and onto the wafer. The second possibility, electrolytic plating, uses the wafer as the negative terminal of a power supply and a similar bath. But instead of a reducing agent supplying the necessary electrons, it is the power supply that does the job together with another electrode that completes the electrical circuit. Despite being the betting favorites, CVD and electroless plating encountered severe problems. "The technology that worked was electrolytic plating," says Panos Andricacos, whose team of electrochemists at Watson and their colleague from East Fishkill, Cyprian Uzoh, pioneered the new methodology. "It has a faster rate of deposition and the evenness of the copper film is better."
In fact, electrolytic plating had a strong pedigree at Watson. Romankiw had used this technique in his early work. Then, in the late 1980s, Andricacos' group had developed electrolytic plating in a different context: applications in chip packaging. The group then attacked the more difficult problem of plating submicron wires on silicon wafers, and soon contributed to a growing knowledge of how to plate very fine wires.
Heidenreich remembers the surprising nature of the choice. "When the project started there was no way in the world we would have thought of electrolytic plating for copper with these dimensions," he says. "Some people thought the copper patterns would be filled with bubbles, or that the process was too 'dirty.'" Since then, Andricacos and his colleagues have focused on readying the technique for use in the ultraclean chip fabrication facilities known as fabs. Uzoh, meanwhile, took plating to a fab - East Fishkill's ASTC.
The Damascene Contribution
A few years before those events, a small team of IBM engineers that included Luther had invented a key technology for patterning thin films of metals, including copper. Called damascene in reference to the metallurgists of old Damascus who produced the finest polished swords in the medieval world, the technique was initially used to form "vias" - the small metal plugs that link separate layers of wiring in chips.
In conventional deposition, a layer of metal and a layer of a masking material called photoresist are deposited on a silicon wafer. Unwanted metal is then etched away with an appropriate chemical, leaving the desired pattern of wires or vias. Next, the spaces between the wires or vias are filled with silicon dioxide (an insulator), and finally the entire wafer surface is polished to remove excess insulator. Damascene patterning involves the same number of steps, but reverses the order of deposition. The pattern of wires or vias is first formed by etching the oxide. The metal is deposited second, and the excess is removed by polishing. In both conventional and damascene patterning the process is repeated many times to form the alternating layers of wires and vias which form the complete wiring system of a silicon chip.
In the early 1980s, IBM's 4-megabit DRAM program combined the wire and via damascene process into so-called dual-damascene technology. This process is regarded as one of the critical advances and key enablers in the development of copper technology. The fact that IBM had years of experience in such processing gave the company a significant leg up on the way to copper.
The dual-damascene process starts out with a deposited layer of oxide, which is etched twice to form the overlapping pattern of wires and vias before the metal is applied and polished. That eliminates one metal deposition step and one polishing step from the process of creating circuitry. "Going to dual-damascene with copper has significant cost benefits, and reduces the number of process steps needed to form the structure," says Jim Harper, manager of thin film metallurgy at Watson.
Applying the technology to copper required a further stage: a way of polishing copper at an acceptable rate while controlling corrosion, erosion and other defects in the patterns. Watson researchers Frank Kaufman, Vlasta Brusic and Naftali Lustig pioneered a chemical-mechanical process that proved critical to IBM's success with copper technology.
Another challenge remained: overcoming copper's tendency to diffuse in silicon. In 1984 Dale Pearson, Hu and others at Watson set out to devise a substance that would act as a diffusion barrier, preventing atoms from migrating out of a copper wire into surrounding chip material. "We worked on several materials, but one particularly stable metal emerged as a very good candidate," says Hu. By the late 1980s, the team had adapted the damascene process to deposit that diffusion barrier in silicon wafers along with copper.
Moving Toward Manufacture
By 1993, the team working on the copper project saw light at the end of the via. To be fully accepted, though, the technology needed an internal customer - an IBM division that would underwrite the project and would assess how it could be adapted for full-scale manufacturing at a reasonable cost. "Without a customer, and a customer's requirements, you can't build a product," emphasizes Luther.
The Microelectronics Division was interested in the copper process, but it was suspicious of the use of polyimide as the insulator, because it tends to be cut and scratched by damascene polishing. In addition, research at the Almaden Research Center had shown that polyimide was not as effective an insulator as originally thought.
The team decided not to try changing both the metal and the insulator together. In late 1993, it was suggested that it would be better to deposit copper on the familiar silicon dioxide insulator, using the dual-damascene process. "That would save money for CMOS manufacturing and also improve reliability and yield," says Edelstein.
When the team put this process to the test, adds Edelstein, "the first few wafers we made were of higher quality than those with polyimide." Even better news followed when the group processed larger wafers in the test facility at the ASTC. "It began to look as if copper could be made to work," says Edelstein. By that time, the performance of CMOS technology had improved to the point at which aluminum circuitry was reaching its limit. Copper plainly beckoned.
The Microelectronics Division agreed. But much remained to be done before copper would be ready for full-scale fabrication. Neil Poulin, a manager in manufacturing at Burlington, compiled a list of nine tasks to be completed before Burlington would accept the technology. "The list, called Poulin's nine commandments, dealt with business issues, such as appointing a single manager to integrate the pieces of the project, and getting vendors to provide tools at the right time," recalls Tom Theis, senior manager of silicon science and technology at Watson. "The items were not typical of what we deal with in Research, but we realized that every one of them was critical." John Heidenreich was made manager and over the next six months, adds Theis, "he essentially addressed every issue."
Late in 1994, the team moved the entire project into the ASTC fab, to work on pilot-scale preparation of chips with copper circuitry. Inevitably, more problems surfaced. Heidenreich had to persuade vendors to adapt their plating tools to the copper process without explaining precisely what the process was. In addition, the team had to respect the fear that copper would contaminate the fab. "There had been some close calls and we had to put together a regimen for dealing with copper," says Heidenreich.
Close collaboration with an ASTC team headed by Jim Ryan helped to solve the problems. Dedicating some tools to copper only and monitoring and cleaning tools shared between copper and aluminum chip making addressed the concerns of other groups in the ASTC, and the project moved ahead at full speed. "We basically started putting all the resources into place," adds IBM Fellow Bijan Davari, Microelectronics Division (IMD) director for advanced logic. "We brought all the processes to ASTC as soon as possible. It was a heroic effort."
The rapid progress convinced Kelly and other senior managers by late fall 1995 not only that copper would work successfully but that the project should be accelerated. "We went to [IBM chairman and CEO] Lou Gerstner to ask for additional funding. We told him that we must do this to lead the industry," says Kelly. "He made a very rapid decision to fund it."
Applications And Enhancements
CMOS 7S will find its first major applications in high-end server data processing and custom logic machines. IBM also expects to include switching systems and telecommunications systems, which require high bandwidth and speed, among the early users of the copper technology, and to use the process to optimize its Power PC chip technology. The industry has responded strongly to the announcement of the technology. "We're being flooded with requests," says Isaac. "People want to migrate to our products." To help satisfy that demand, the company has announced chip-design kits that customers can use to generate their own designs of application-specific integrated circuits (ASICs) based on copper, for manufacture by IBM. The company is also pursuing the possibility of organizing industrial partnerships based on the new technology.
"Meanwhile, Research is still involved with the move to manufacturability, while continuing to work on the next cycle of the technology," says Theis. Subjects under investigation include enhanced electroplating methods, different insulators and better understanding of electromigration in copper. "The extendability of the technology is immense," declares Romankiw. "I can see no limit."
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