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To: Gary Ng who wrote (82856)	6/6/1999 2:55:00 AM
From: Tenchusatsu	Respond to of 186894

<What I don't understand is that why don't they just put on-CHIP L2 in K7 right from the beginning ?> K7 die size is too large even without the on-chip L2 cache, at least on the 0.25 micron process. AMD is hoping that the oversized 128K L1 cache will reduce the need for an on-die L2 cache. Tenchusatsu

To: Gary Ng who wrote (82856)	6/6/1999 9:54:00 AM
From: Paul Engel	Respond to of 186894

Gary - Re: ". What I don't understand is that why don't they just put on-CHIP L2 in K7 right from the beginning ? They are doing it in K6-III, aren't they ?" This is EXACTLY why I said "AMD is going to look PRETTY STUPID - introducing an EXPENSIVE Slot A K7". Get it NOW ? Paul

To: Gary Ng who wrote (82856)	6/6/1999 10:01:00 AM
From: Cirruslvr	Respond to of 186894

Gary - RE: "What I don't understand is that why don't they just put on-CHIP L2 in K7 right from the beginning ?" The K7 is already big. People here have said that the size of L2 cache has to be at least 4X the size of the L1 cache. That means the L2 cache of the K7 would have to be at least 512K. On the .25 process, if 256K L2 cache adds 37mm2 to the size of the K6-III, 512K L2 cache would add 74mm2 (assuming I can just double the amount and not worry about other stuff). That would make a .25 process K7 with 128K L1 cache and 512K L2 cache 258mm2. That is big, and the people here who know, say the bigger the die is, the lower the yield is. On the .18 process, the story is a little different. PB has calculated that 512K L2 cache would be about 35-40mm2. That, in addition to the approx. 105mm2 the K7 is going to be, will still make the K7 kind of big, but still smaller than it is now on the .25 process, and still smaller than the Celeron is today. Maybe AMD will come out with a K7"-2" w/512K on chip L2 cache next year to help better compete with Willamette.