VSIA remix:
Nokia takes VSIA standards on the road for 3G work
Message 13822468
In mobile communications, it's important to develop design methodologies that shorten the time-to-market and support the rapid creation of design derivatives. So Nokia Research Center and its development partner, InterDigital Communications Corp., have been developing system-level design methodologies that employ reusable virtual components. Now they have teamed with EDA provider CoWare Inc. to test new Virtual Socket Interface Alliance (VSIA) standards using a 3G cellular pilot project......
IP reuse called essential to advanced chip designs
Message 13853172
.....But in the IP space, disparate consumer products that span the video, audio, and telecommunication markets will not allow de facto standards to be set by one or two companies, Claasen said. Application-specific platforms will emerge that will each need to be uniquely characterized by computational speed, power requirements, real-time versus non-real-time system constraints, form factor, and cost.
[comment: Nokia/IDCC/CoWare seem to be between 3rd and 4th generation, if I'm not mistaken. This makes sense if you consider that Nokia is going to exceed 100 million handsets this year or next year and they probably want to maintain a very high degree of commonality of parts - currently at 70-80%]
Therefore, the third generation of IP now emerging is architectural, according to Claasen. Philips Semiconductors is now using such a flexible platform, he said. In addition, rapid silicon prototyping will be crucial to validating the architectural IP at a pace required by time-to-market demands, he said.
Finally, Claasen called "IC reuse" the fourth and ultimate generation of IP reuse. When the industry is working to achieve 100-million-plus transistor chips and masks have grown prohibitively expensive, it will be impossible to synthesize silicon if any possibility lingers of design error, specification error, or manufacturing variations. Therefore, silicon efficiency will mandate compiler and computational efficiency, reconfigurable interconnects, and on-board software, which in turn will open the way for complete IC reuse, according to Claasen.
Claasen concluded by stating that design efficiency is in danger of not keeping pace with Moore's Law and process technologies. The next generation of reuse technologies will be dependent on solutions that . And IP reuse is coming of age as architectural reuse emerges as a reality, he said.
The final word in IP reuse will involve IC reuse and retargetable architectures: a technology that may never come to pass, Claasen said.....
VSIA develops system-level modeling standards
eedesign.com
The Virtual Socket Interface Alliance wants to improve the understandability and integration of the system-level design process. So it has formed the System-Level Design Development Working Group to build upon the VSIA charter to streamline the virtual-component authoring-for-reuse and system-on-chip integration processes..........
Levels of system design
VSIA's system-level design concept includes three basic abstractions of design refinement for an SoC: a cycle-true representation of the chip, a cycle-approximate model abstraction and a behavioral abstraction.
Cycle-true is equivalent to the standard RT level description of a component, permitting validation of the operation on a clock-cycle basis. Although accurate, this level of abstraction is extremely slow to simulate and cannot be built until the system and all its components are well defined. This is often referred to as the "implementation level" of design.
Cycle-approximate, or partially cycle accurate, implies tying actions to the concept of a "tick" but not at the granularity of clock-cycle boundaries. By allowing packetizing of data into more complex data structures and providing for partially independent execution of blocks such as through instruction set simulation to HDL cosimulation, faster simulation is made possible by trading against clock-cycle accuracy. Not all architectural elements need to be defined in detail so assembly of this abstraction can occur earlier in the design process, thereby allowing a broader range of architectural exploration.
Behavioral, or functional, modeling describes the intended function of the system with minor or no architectural considerations taken into account. When used for temporal performance estimation, these models communicate asynchronously with a "delay-line" view of time providing only coarse performance assessment but allowing assessment of functional intent. Connection between objects at the behavioral level expresses the communication principle rather than implemented protocol. This layer and its early mappings are critical in the exploration of functional and architectural options.
System design as a process is the flow from the behavioral or functional description of an application, through architectural mapping and performance modeling, to cycle-accurate block assembly and verification. It must not only ensure that the design remains consistent as it is refined, but must also allow the concept of mixed-mode simulation whereby functions at any level of abstraction can be simulated together.
The guarantee of design correctness throughout system abstraction refinement can be broken into the following principles: definition of model field of use (FOU), expression of communication, expression of functionality, SoC verification and validation.....
More on CoWare:
CoWare, Inc., founded in 1996, provides system-on-a-chip software to meet the growing demands of today's IC designers. The CoWare N2C design system enables designers to take their concepts from "napkin-to-chip" in half the time required by traditional IC design methods, and had been proven in customer designs ranging from consumer electronics to next-generation multimedia devices to telecommunications equipment. CoWare is headquartered in Santa Clara, California.
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