GS US SEMI EQUIP SEMICON WEST DAY TWO: KLA, TEL AND INTEL DOMINATE THE HEADLINES
Summary: We attended the 2nd day of SEMICON West on Tues. Key takeaways are: (1)
KLA reporting flat June orders (within guidance range but below Street expectations),
Tokyo Electron guiding CY2005 Japanese capex flat y-o- y, and Intel's inventory and
margin issues drove a continued muted tone at the show. We believe wafer-start driven
stocks will be weak as a result of Intel's forecasted production slowdown but we do not
believe that Intel's capex plans will be disrupted by its inventory overhang as INTC's
capex has historically been driven by technology transitions as opposed to utilization
rates, (2) TEL highlighted that it has won recent 65nm dielectric etch orders head-to-head
against LRCX, (3) Axcelis management suggested that its new 65nm single wafer
implanter has not been delayed, and (4) Presentation by STC highlights back-end
opportunities for open architecture initiative.
MORE OF THE SAME ON DAY TWO OF SEMICON WEST AS NEWSFLOW
CONTINUES TO BE LESS ROBUST THAN EXPECTED. We attended the second day
of SEMICON West (SW) in San Francisco, CA on Tuesday. Recall that SW is an
industry trade show sponsored by SEMI (an industry trade association). The front-end
manufacturing portion is being held through Wednesday in San Francisco and the
back-end portion will be held from Wednesday through Friday in San Jose. Tuesday's
newsflow was dominated by presentations from KLA-Tencor, Tokyo Electron, and of
course, later in the day, news from the Intel earnings release. We also met with Brooks
Automation, Axcelis, Entegris, MKS Instruments, MEMC, and Mykrolis. While semi
equipment management teams maintained their bullish tone, similar to day one, we
believe that the newsflow from the second day of the conference was quite disappointing
relative to expectations heading into the show.
We provide our key takeaways from our second day of meetings below:
(1) WHILE MOST SEMI EQUIPMENT MANAGEMENTS REMAINED BULLISH,
THE OVERALL TONE OF THE SHOW WAS AGAIN DISAPPOINTING RELATIVE
TO HEIGHTENED EXPECTATIONS HEADING INTO THE WEEK WITH FLAT
ORDERS FROM KLAC, SUBDUED COMMENTS ON CY2005 JAPANESE CAPEX
FROM TEL AND INTEL'S MARGIN AND INVENTORY ISSUES WEIGHING ON
SENTIMENT. It appears as if the upbeat outlook for which the Street so desperately
hoped heading into this year's show will not materialize as day two of the front-end
portion of the conference remained subdued due to lower than expected CQ2 orders from
KLAC and guidance from TEL that CY2005 Japanese capex would be flat
year-over-year. In addition, news from Intel of higher inventories and lower margins did
little to turn the apathetic mood of conference attendees.
While many management teams suggest that visibility remains strong through H2'04,
there seems to be much less conviction regarding the duration of the cycle than there was
even three months ago. We believe this is due to some combination of newsflow
upstream in the tech chain, negative Street chatter and the resulting decline in company
stock prices. Although managements will not comment on the topic directly in formal
presentations, we believe one of the issues driving what we believe to be lower conviction on the
duration of the cycle is Samsung's capex plan. After its first quarter results, Samsung had given
strong indications to its equipment suppliers that it was likely to increase its 2004 capex
significantly, perhaps by as much as $1.0 to $1.5 billion. Without providing detail, Samsung
provided similar indications to us in a group luncheon which we attended several months ago after
which we published a note indicating that we believed that there was likely significant upside to
Samsung's original 2004 capex budget. We have spoken with several contacts at the show who
have indicated that Samsung now looks much less likely to increase its original budget due to a
demand slowdown over the last few months. We believe this change of tone from Samsung to the
equipment suppliers is driving at least part of what we perceive to be lower conviction around the
duration of the cycle.
Regarding the Intel news, we do not believe that investors should be overly concerned about a
reduction in the company's 2004 capex budget or its indication for meaningfully higher capex in
2005 despite its indication on its earnings call that production volume will slow in the coming
quarters to work down excess inventory. Recall that Intel's capex has historically been driven by
technology transitions rather than capacity utilization. For example, even during the depths of the
downturn in 2001, Intel spent a record $7.3 billion as it made its early move to 300mm wafer sizes.
We believe Intel's 2004/2005 budget will continue to be driven by the 65nm linewidth shrink and
will likely remain intact barring another significant disruption to its business.
The Intel news is likely not as benign for the companies whose business is driven at least partially
by wafer starts, including ATMI, ENTG, MYK and WFR, all of which could be weak in the
near-term as a result of Intel's decision to decrease volume production in the coming quarters.
While we believe these companies remain amongst the most attractive over the course of a full
cycle due to their cyclically more stable wafer start driven model, investors will likely not be
anxious to approach stocks with a multi- year time horizon in the immediate future as Intel's
announcement could have negative near-term implications for CQ3 operating results for the
wafer-start driven companies.
(2) TOKYO ELECTRON HIGHLIGHTED THAT IT HAS WON A RECENT HEAD-TO-HEAD
MATCH AGAINST LAM RESEARCH FOR 65NM DIELECTRIC ETCH ORDERS WHICH
STREET CHATTER HAD PREVIOUSLY AWARDED TO LAM. During its analyst meeting,
Tokyo Electron highlighted that recent stories of share loss at a major US IDM were unfounded as
it asserts that it has won 65nm dielectric etch orders at this customer. Further, TEL showed
company estimates which indicate that it is gaining share in the dielectric etch segment, although it
did not comment on whether it believes those share gains are coming at the expense of Lam or
Applied Materials.
(3) AXCELIS MANAGEMENT WAS ADAMANT THAT ITS 65NM SINGLE WAFER, HIGH
CURRENT ION IMPLANTER WILL BE AVAILABLE FOR BETA SHIPMENT IN Q4'04 AS
PREVIOUSLY PLANNED. In our note from yesterday's conference, we had reported that a
conversation with a channel contact indicated that the new 65nm single wafer, high current ion
implanter which Axcelis had discussed at its analyst meeting several months back would not be
available before Q1'05. Axcelis management vehemently disagreed with this assertion as they
continue to stand behind their previous statement that a beta tool will be available by YE 2004.
This is a debate which we will monitor closely over the coming months as Axcelis is currently the
market share leader in the high current segment but we believe that this position could be at risk if
the timing for the tool were to slip.
(4) PRESENTATION BY STC HIGHLIGHTS BACK-END OPPORTUNITIES FOR OPEN
ARCHITECTURE INITIATIVE. While the back-end portion of the show doesn't officially begin
until Wednesday afternoon, we attended a dinner hosted by the Semiconductor Test Consortium
(STC) on Tuesday night during which the STC provided an overview of its strategy and an update
on its progress. Recall that the STC is a non-profit industry group led by Advantest that is
dedicated the development of an open architecture SOC test platform. The Open Architecture
platform consists of a mainframe tester supplied by Advantest (called the T2000) which can be
modified based upon customer requirements for price and performance with off-the-shelf modules
supplied by members of the consortium. Including the module vendors, the consortium currently
consists of 39 members (1 member was recently added to the consortium), including 6 of the top 10
semi device companies (Intel, Freescale, Toshiba, Analog Devices, Renesas, Fujitsu, and Philips)
and 11 educational institutions.
The Open Architecture platform was developed to address the increasing number of different
device types requiring testing and the complex test requirements of those devices (and, of course,
the corresponding high cost of test). The STC hopes to address the high cost of test by providing
customers with an open architecture tester that allows semi device companies to only pay for
needed functionality, to have lower hardware/software training costs, greater hardware/software
reusability, lower infrastructure costs, greater utilization, greater scalability, and longer test system
life cycles. Our impression from the STC dinner on Tuesday night is that module vendors are
excited about their ability to contribute to the consortium, as it allows vendors greater R&D
leverage and
a larger addressable common market.
The open architecture platform has been used thus far primarily by Intel (which has highlighted a
60% cost reduction by using the platform) and is therefore criticized by other test suppliers as being
primarily applicable to microprocessor chips. However, the platform was designed to address
various segments including chipsets, MCUs, and ASICs. Advantest has indicated that it expects the
open architecture platform to gain even greater traction in the next 12 months with Intel potentially
receiving less than 50% of systems shipped after that time (thus mitigating the criticism that the
STC is only providing testers to Intel). We would look for the consortium to continue to add device
companies to its roster (STMicro is speculated to be heavily considering joining the consortium) as
a sign of its increasing prevalence and importance in the test market, as a device company joining
the STC implies an interest in aligning technology roadmaps with the consortium and therefore an
interest in eventually investing in the open architecture platform.
I, Jim Covello, hereby certify that all of the view |
