SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : CYRIX / NSM
NSM 18.270.0%Jul 31 5:00 PM EST

 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: Scumbria who wrote (29880)10/13/1998 10:24:00 PM
From: Joe NYC  Read Replies (1) of 33344
 
Scumbria,

Would you care to comment on couple of my questions on AMD board:

Message 6002558

from pdf:

7 clock access latency for L2

Is this good, bad or average?

Message 6002947
K7
Two General Purpose 64-bit Load/Store Ports into D-Cache
- 3-Cycle Load Latency
- Multi-banking Allows Concurrent Access by 2 Load/Stores


M3
16K, 4-way, non-blocking data cache (3 cycle access, 1 load port, 1 store/fill port

What are the differences between these 2?

Joe
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext