Novellus Message Board - Msg: 6780693

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Technology Stocks : Novellus

NVLS 2.400

+2.1%

Jul 24 5:00 PM EST

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To: Artslaw who wrote (1685)	12/10/1998 6:18:00 PM
From: FJB	Read Replies (2) of 3813

Steve, RE:Just one quick comment. I don't follow Intel's processing too closely (they don't talk much about it anyway), but I'm pretty sure that if they say they have a 0.18µ process, they don't have 0.13µ physical gates. They might have 0.13&mu effective channel lengths (the distance the electrons (in nMOS) have to travel from one side of the transistor to the other). This is because(among other things) the source and drain (the contacts on either side of the channel) undercut the gate. This is usually on purpose now since they have a shallow 'tip' region, but in the old days more due to uncontrollable lateral diffusion. I hate to be a tremendous pain, but concerning your comments, there is somebody that differs with your opinion. Intel uses terminology I have not heard before like LGATE. Anyway, this gentleman thinks the Leff is 0.08 for Intel's newly announced "0.18" process. I'm not qualified to make heads or tails of it. Here are the references: Message 6766898 Message 6744607 eet.com If you could clarify the terminology for me, I'll send you a case of your favorite beer for Christmas. I can imagine the cross section of a transistor and I've seen the SEM pictures of them. Is measuring from the outer edge the drawn gate length and from the inner edge the Leff? Bob

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