Overall Process for the wafer, which makes it almost immeasurable over each layer. I never said that it was definitive and could be traced back to a specific step or level since the volumes of electrical data to analyze makes it almost impossible.
Now a theory, is that Gate Oxide integrity (the gate oxide below the transistor Poly level)could be the root but it is inconclusive. IT makes sense from the stacking fault and/or overall impurity levels of the silicon itself. However, it could just as easily be something as simple as flatness across the wafer giving better litho resolution.
The same type of issues held true when we evaluated chemicals from various vendors. We would get C of C (certificates of Compliance) data showing purity levels down to the ppm and ppb levels. No one had the diagnostic equipment in house to verify the C of C but functional testing would result in minor yield differences across split lots, that would support going with one vendor over another.
All in all, we are talking about the old adage, "the pennies add up".
There are 16-24 photolith steps alone and if one photoresist had a ever so slight resolution edge over another, or had a slight bit more process latitude, it could be seen over the course of all layers processed over time. In the case of photoresists we did have the electrical testing of transistors on flat poly test wafers to better quantify any improvements before moving the experiments over to actual production wafers.
The pennies do add up. If a DRAM sells for $10 and you have 200 die (conservative) per wafer, a 1% yield increase is 2 die per wafer and $20 more revenue. However, it is not only the extra revenue and profits that are made with this yield increase, it is also the question of cost or capacity.
If your fab is not running at capacity, you lower die cost per wafer by a few bucks, which improves margins. If you are running at capacity, you now have an extra 1-2% equivalent of wafers starts without even starting more wafers.
Andrew |
