Battered wafer suppliers face an uncertain future
By J. Robert Lineback and Will Wade
SAN JOSE -- Memory isn't the only semiconductor market today where prices are lousy and profits non-existent. With chip makers' inventories of production wafers still bulging, blank wafer suppliers are drowning in a sea of red ink. The wafer glut was so bad last year that the world's producers of blank silicon wafers together lost nearly $1 billion on sales of $5.6 billion. That grim estimate comes from Daniel J. Rose of Rose Associates, who sees "absolutely no light at the end of the tunnel" for wafer suppliers.
To make matters worse, no one seems to have a good handle now on which types of starting substrates will be needed most by integrated-circuit fabs during the next decade. A variety of approaches are being taken now to improve the quality of silicon. Next-generation chip making will require higher levels of crystal purity.
Some suppliers have started promoting so-called "perfect" silicon wafers that are made from high-purity ingots. But they cost more than today's prime production wafers because the crystals are grown at much slower rates to eliminate defects.
A lower cost alternative to perfect silicon involves depositing a thin layer of high-purity epitaxial silicon over lower priced, low-grade substrates. There is no indications yet as to whether IC makers will embrace these epi-optimized substrates (EOS). And if they do, it's unclear just who would pocket the cost-savings - the silicon supplier or chip maker.
Wafer merchants also are trying to figure out what the future demand will be for silicon-on-insulator (SOI) substrates. Last year, IBM Corp. pushed SOI into the limelight when it announced aggressive plans to use this kind of wafer in volume production. The company's aim was to boost IC performance yet still cut power consumption by as much as 50% (see story in the Sept. 1, 1998, publication of SBN).
But the major drawback with SOI is still its high price tag. It's not clear just how fast suppliers can drive down the cost of SOI wafers, which are currently priced from six to 10 times higher than standard prime silicon substrates.
At the same time, blank wafer suppliers still face the daunting task of pumping out production-worthy 300-mm wafers when chip makers finally begin their long awaited but delayed transition to larger-diameter substrates. Production of high-grade 300-mm starting wafers is expected to be costly and slow, according to some materials analysts, if such new materials as epi-optimized substrates aren't used to enhance silicon surface areas to accommodate feature sizes of 0.13-micron and below.
But wafer suppliers have a far more important challenge now than to try and figure out what kind of future products their customers will need. First they have to survive.
"We're not making any money, and if anyone else in this industry says they are, I would have to question their sanity," laments Robert Gill, chief operating officer for Sumitomo Sitix Silicon Inc., the U.S. subsidiary of the world's largest wafer supplier.
Despite the rebound in chip sales in the last half of 1998, most wafer suppliers don't expect any relief from the wafer glut or depressed silicon prices until late next year. Analyst Rose, who has just finished surveying the seven Japanese wafer manufacturers, says that "we now see how much red ink is flowing out there. Things are extremely bad across the board," acknowledges the Los Altos, Calif.-based Rose, "and most Japanese suppliers are projecting continued tough conditions for the next 12 to 24 months." MEMC Electronic Materials Inc. also continues to hemorrhage badly. In late April, the U.S.-based wafer supplier reported a net loss of $50.3 million on sales of $159.8 million for the first 1999 quarter. This continues more than two years of losses for the world's second largest wafer supplier. MEMC reported a net loss of $194.6 million on revenues of $758.9 million last year and a net loss of $6.7 million on sales of $986.7 million in 1997.
Conditions have gotten so bad in fact that even competitors in this market now have begun to work together to share costs. In early April, Mitsubishi Materials Corp. and its Mitsubishi Materials Silicon Corp. subsidiary announced a joint-venture with Sumitomo Metal Industries Ltd. in Japan to pool their resources for 300-mm wafer production. The effort is slated to begin in July.
"With Sumitomo and Mitsubishi joining forces," Rose says, "it's a real testimonial to how difficult the situation has become. The primary factor, [according to the two suppliers], is rising costs." For example, he notes, "it will cost $500-to-$600 million [to build a] 12-inch facility capable of producing 100,000 wafers a month." The cost to build a fab now to turn out the same number of 8-inch wafers, he says, is less than half as much, or $190-to-$220 million.
But even with the lower costs of turning out the smaller wafer, silicon suppliers have been losing their shirts. One big reason: They badly miscalculated demand when a silicon famine hit the industry in the 1994-95 boom market and simply built too much production capacity.
-MEMC's De Luca
Until that silicon glut developed, suppliers were making most of their profits from epi wafers, which were priced about 30% higher than standard polished prime wafers. These epi wafers come with a thin layer of high-purity silicon deposited on a prime substrate. The enhanced wafer was used by fabs to boost production yields and the performance of advanced ICs such as microprocessors. It was the fall of prices for these enhanced wafers that has most hurt suppliers recently. Average selling prices for 200-mm epi wafers tumbled from $160-to-$180 in the last half of 1997 to $95-to-$130 in the first half of 1999, according to Rose. These prices won't level off until next year when epi wafers will be selling for about $90-to-$120 each, he predicts.
These falling wafer prices are causing chip makers to re-evaluate their use of substrates. In some cases, chip makers are reconsidering the use of epi after switching earlier to lower priced prime polished substrates to save money.
"Cost drives wafer selection, and with the differential between epi and prime going away, some companies are reconsidering their decision to move away from epi," comments Rick Wise, diffusion implant manager in the Kilby Center development fab at Texas Instruments Inc. in Dallas. "We are now considering all the options for the future, including 'perfect' silicon, low-cost epi, and SOI."
But chip makers don't want to go running off in all directions so they are limiting the variety of wafer types they are using. "We are moving towards lower defect wafers but we want to maintain our part number set and wait to see what the benefits are before moving to something like perfect silicon or epi-optimized substrates," explains Bob Bendernagel, manager of silicon wafer procurement at IBM Microelectronics in East Fishkill, N.Y. "Right now we try to keep it as simple as possible so we can share inventories [among wafer-processing frontend lines]." Many IC makers have avoided having to make a switch to the higher cost epi wafers by adding a high-temperature hydrogen or nitrogen annealing step to eliminate defects on their prime wafers. This has enabled them to use these low cost wafers for some advanced chip products. The thermal process rids silicon surface regions of device-killing voids, which are known as crystal originated pits (COPs). Eventually, however, advanced wafer processing will require higher levels of purity in the active regions of silicon chips, forcing a move to the higher grades of silicon crystals.
To achieve this greater purity but hold down production costs, some wafer makers are now promoting the use of epi layers on lower grades of silicon substrates, which can be grown at faster rates than today's prime production wafers. "The crystal can be pulled three times faster and the substrate can have a wider spec for resistively or oxygen [content] because epi is used to produce the active layer for devices," explains Malcolm Russ, an advocate of epi-optimized substrates who is principal consultant to MJR Technology in North Plains, Ore. "The starting wafer becomes a cheaper mechanical substrate for epi."
-Saitec's auberton-Herve
Russ figures that the cost of high-purity silicon could be cut in half by going this route. "The crystal growing business is the same now as it was 20 years ago," he notes. "It needs a paradigm shift [like this]. It needs shaking up." Some silicon suppliers already have started offering EOS wafer samples to chip makers. Sumitomo Sitix is now shipping small volumes of epi-optimized substrates, says Gill, who is based at the company's Phoenix facility. "It's a viable product for us today," he maintains.
While some chip makers plan to evaluate the EOS wafer, many are still taking a more cautious approach to investigating the concept.
"My concern is that the substrate is not completely independent of the circuit," points out K.V. Ravi, silicon technology manager for Intel Corp. in Santa Clara, Calif. "We cannot completely throw out the fact that the substrate has some important attributes." The EOS wafer is a "good idea," he says, "but it [still] needs to be fleshed out."
Other silicon suppliers are putting their money on the higher-purity prime wafers in the hope of leveraging volumes to drive down costs. MEMC is a strong advocate of "perfect" silicon, and the company aims eventually to offer wafers with the purity and performance levels of epi substrates but at a lower cost, says John De Luca, vice president of technology at the St. Peters, Mo., company.
MEMC already has started shipping low volumes of perfect silicon wafers to its customers and is prepared to ramp up production when demand is there, De Luca says. The MEMC vice president believes that perfect silicon most likely will be used in advanced memory fabs while most logic makers are expected to continue using epi wafers. This is because heavily-doped substrates are needed to prevent latch up.
"Perfect silicon is an advanced wafer solution, [but] it's not meant to be used by everyone," De Luca adds.
Other wafer executives are quick to point out that both perfect silicon and EOS have a long way to go before they are mainstream substrates for volume chip making. "Having a slower pulling process limits [perfect silicon] productivity," points out John Matlock, president and CEO of Komatsu Silicon America Inc. in Hillsboro, Ore. He believes that epi-optimized substrates is a good idea but that it will require additional investments from cash-stripped wafer suppliers in order to move into volume production.
SOI wafer makers may also stand to gain from current efforts to create perfect silicon and epi-optimized substrates. Silicon-On-Insulator Technologies SA (Soitec), based near Grenoble, France, is looking to bond perfect silicon wafers to lower-purity substrates using its Smart Cut process for SOI.
The way this works, Soitec will grow insulating oxide layers on top of perfect silicon wafers from its Japanese partner, Shin-Etsu Handotai Co. The perfect wafer then is bonded to a low-purity wafer, creating a sandwich of oxide between the perfect silicon and a mechanical silicon substrate. A cutting region is created in the perfect silicon wafer by high-current ion implantation.
After the cut, a thin layer of perfect silicon is left on top of the oxide, creating high-purity SOI wafer. Soitec's process allows it to reuse a single perfect wafer up to a hundred times to make SOI wafers with lower-cost substrates.
This combination of perfect silicon and lower-grade silicon substrate should help to cut the cost of SOI by about 30%, estimates Andre Auberton-Herve, president and co-founder of Soitec.
"Today, we are using low-COP wafers, which are not yet perfect ones," he notes. Perfect silicon is "the next step and we plan to do this later this year and begin shipping products in 2000."
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