Date: 07/10 23:50 EST
SoC era puts equipment makers to test at Semicon
Jul. 10, 1999 (Electronic Engineering Times - CMP via COMTEX) -- San
Jose, Calif. - The Semicon equipment makers' show opens here this week
amid growing concerns about the difficulties of testing the emerging
crop of submicron ICs and fast microprocessors and memories. Such chips
can carry both digital and analog functionality or clock rates
approaching the gigahertz region.
Over the last few years, the major ATE vendors-including Advantest,
Credence, Hewlett-Packard, LTX, Schlumberger and Teradyne-have come up
with a variety of solutions, including specialized testers, all-in-one
machines and special add-on equipment to handle, say, microwave chips
or Rambus memories.
But the capabilities expected to roll out at Semicon show that test
has become a Hydra-headed monster: As soon as one problem is licked,
another crops up.
Some of the more interesting rollouts are coming from Hewlett-Packard
Co., Advantest and Schlumberger Automated Test Equipment.
HP says it can meet the volume-production test challenges of highly
integrated system-on-chip (SoC) devices with a new family of systems
that combine the best of HP's high-speed VLSI and low-noise
mixed-signal testers. Advantest's twist leans on extreme compatibility
between an existing tester used for engineering characterization and an
SoC-test unit that will see first light at Semicon. And Schlumberger
ATE is attacking a problem newly bedeviling the speedy microprocessors
now emerging from Intel and others: self-heating.
Scalable platform
The HP 93000 SoC Series Performance Models employ Hewlett-Packard's
pay-per-use technology, which permits frequency and pin counts to be
upgraded as needed. Data rates can reach as high as 1 Gbit/second. The
Series C-Models, offering several fixed configurations and lower
frequencies, are aimed at lower-cost, less complex devices. Both will
support test heads containing up to 448 or 960 digital pins and space
for up to four analog modules.
"HP's scalable platform approach will help SoC manufacturers reduce
the cost of test by increasing the productivity of test engineers and
minimizing initial investment," said Ken Neff, president of Prime
Research Group, a Florida-based research firm.
Initial devices targeted by the new HP family include microprocessor
cores, such as PowerPC, ARM and MIPS; DSP cores; mixed-signal blocks,
such as D/A and A/D converters; high-speed serial communication
interfaces like 1394, Fibre Channel and Panel Link; and high-speed
parallel buses, including PCI, PCI-X, AGP4x, LVDS and Rambus. Other
target chips are ASICs, memories, multimedia ICs and similar
high-pin-count devices.
"Our new test family is the culmination of three years of extensive
collaboration within our newly formed Silicon Systems Test Division,"
said John Scruggs, HP vice president and general manager of the
Automated Test Group. "We've designed the series to give our multimedia
and SoC customers, who are sensitive to production costs, an extremely
versatile platform."
SoC manufacturers increasingly need a production tester that can
handle embedded memory, analog functions, communications interfaces,
high-speed buses and digital content simultaneously.
Toward that end, the new HP tester line features data rates from 600
to 1,000 Mbits/s (a low-cost, 400-Mbit/s version is slated to show up
next year). Standard configurations incorporate 960 digital channels,
with four analog slots, and 448 digital channels, also with four analog
slots. A test-processor-per-pin architecture also carries integral
analog instruments.
For its part, the new Advantest contender, the T6672, takes aim at
ASICs or SoCs that require testing of embedded memory, large scan
patterns or mixed-signal features. The system also can be used for
wafer probing of Rambus, 1394, Sonet or MPU devices, for which it can
provide functional test capability at up to 1-GHz clock rates and
500-MHz data rates. The system has two configurations: single or dual
test stations. The single configuration carries up to 1,024 digital I/O
pins; the dual, up to 512.
The system has complete compatibility with the company's
engineering-characterization tester, a trait that Advantest says can be
important for time and economic reasons. "No other ATE company has this
degree of compatibility between logic test family members," said Rick
Chrusciel, product manager for logic testers at Advantest. "That kind
of compatibility makes moving devices from characterization to
production transparent, with no re-engineering of fixtures or software
needed."
The systems share identical test fixtures and docking interfaces, and
a complement of
options including scan- and algorithmic-pattern generators,
high-speed clock and high-speed pattern server, and mixed-signal
facilities.
Meanwhile, Schlumberger has fixed its attention on a problem cropping
up in the newest MPUs. High frequencies appear to be causing
self-heating of the chip die, with repercussions in measuring chip
frequencies. According to Schlumberger ATE, at 500 MHz, each degree of
die temperature inaccuracy results in 1 MHz of device
operating-frequency error, and a significant loss of precision in
operating-frequency measurements.
Uncertain measurements
Raise the junction temperature of a CMOS device and its maximum
switching frequency goes down. A junction temperature error of 20
degrees C during testing, typical in a high-speed MPU, induces a
frequency-measurement uncertainty of 20 MHz.
Schlumberger's solution is a precision thermally controlled test
handler for design and validation that it claims can
dramatically improve testing accuracy. "Schlumberger has leveraged
its expertise in thermal control to help customers overcome
die-temperature issues" and increase yields, said Jackie Tubis,
president of Schlumberger ATE.
The IHS 1000tx is billed as controlling devices under test up to and
exceeding 100 W/ cm2, eliminating the risk of thermal damage in test
and enabling chip makers to isolate thermal performance variances
quickly and accurately.
Combining the company's Power Balancing thermal technology and a test
handler overcomes the die-temperature issue by providing minimal
set-point deviation during characterization, validation and final
manufacturing test.
"Schlumberger has proven beyond a doubt that self-heating during test
lowers the maximum frequency test result," said Jim Walker, principal
analyst for semiconductor packaging and assembly at Dataquest.
"Further, it has demonstrated that products with Power Balancing can
effectively eliminate that problem, resulting in greater accuracy and
improved speed-grade yield."
At press time, Schlumberger unexpectedly said it would also show its
highest-accuracy VLSI tester at Semicon, a fourth-generation unit with
plus/minus 10-ps timing measurement accuracy and up to plus/minus 35-ps
typical edge placement accuracy over 4,096 timing sets. That accuracy
is delivered right to the device under test by a "to-the-socket"
calibration package.
The ITS 9000KX appears aimed at solidifying Schlumberger's strong
position in microprocessor or logic testing. According to Risto
Puhakka, a vice president at VLSI Research Inc., Schlumberger ATE holds
37 percent of the advanced logic test market, making it "the
established market leader in VLSI device test."
Schlumberger said it has already shipped systems for use in
next-generation MPU and high-speed bus applications.
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By: Stan Runyon
Copyright 1999 CMP Media Inc.
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