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To: unclewest who wrote (24642)7/13/1999 5:54:00 PM
From: Kiriwuth Path  Read Replies (1) | Respond to of 93625
 
Intel Conference Call just confirmed that the Camino chipset is on schedule!

It also mentioned the chipset offers RDRAM or SDRAM. It did not mention PC133.



To: unclewest who wrote (24642)7/13/1999 5:55:00 PM
From: Jdaasoc  Read Replies (1) | Respond to of 93625
 
Unclewest:
I reread this article and came to the realization that RDRAM has won convincingly for any computer under 1 GB or 16-512 MBit chips. Also, the Japanese are on same page in their thinking. Samsung's position cannot be much different. I guess by 2001 they will be complaining about low prices for commodidy RDRAM. They address all important issues:

Complexity = Cost to impliment
Granularity = total % of RAM market addressed


eetimes.com

512-Mbit DRAM finding support in Japan
By Anthony Cataldo
EE Times
(07/13/99, 3:21 p.m. EDT)

TOKYO — Support is growing among Japanese chip makers for the development of 512-Mbit DRAMs, as manufacturers struggle with the economics of mass producing 1-gigabit DRAMs and with meeting the granularity requirements of upcoming PCs.

NEC Corp., Toshiba Corp. and Fujitsu Ltd. each said in recent interviews that they will offer 512-Mbit DRAMs concurrently with 256-Mbit devices. The move is similar to suppliers' current offering of a 128-Mbit DRAM, which is now coming into high volume production, to bridge the 64-Mbit and 256-Mbit generations.

Explaining the interim density, suppliers said the transition from 256-Mbit to 1-Gbit DRAMs will require a bigger process technology leap than expected if production costs are to be kept in line.

"I think 512-Mbit is a good [density] to construct a smaller chip size and to move into a 400-mil TSOP package," said Masao Taguchi, deputy general manager of the DRAM division of Fujitsu (Kawasaki, Japan). Such a chip could also be used in other package types, such as chip-scale packaging, Taguchi said.

Mass production of 512-Mbit DRAMs will probably start at 0.13-micron design rules — the same process technology that will be used for volume production of 256-Mbit DRAMs, Taguchi said.

"Even in the case of 0.15- or 0.16-micron, the [512-Mbit] chip size is at 110 or 100 millimeters squared, roughly speaking," he said. "If we use 0.13 micron, the chip size should be around 50 millimeters squared."

Chip size is among the most important factors in determining the production cost of DRAMs. Following Micron Technology's model, DRAM makers in recent years have turned to chip size reductions, or "shrinks," as the main vehicle to reduce manufacturing costs and boost output.

But the rate at which companies are shrinking their process technologies and the physical limitations they are encountering have caused development costs to skyrocket.

Both Fujitsu and Toshiba agreed late last year to co-develop a 0.13-micron process technology for DRAMs in order to share increasing research and development costs. The companies expect to finish their work by 2001, Taguchi said.

Similarly, NEC and Hitachi Ltd. recently agreed to combine their R&D forces to develop an 0.15-micron process technology for 256-Mbit DRAMs by the fall of 2000. The alliance will also explore ways for the two companies to cooperate on manufacturing and marketing.

When Fujitsu and Toshiba announced their tie-up, there was speculation that the two companies would use the 0.13-micron process technology for the mass production of 1-Gbit DRAMs. Taguchi, however, said a 1-Gbit DRAM built in that process would have a size of 250 millimeters squared — still too large for mass production.

"0.13-micron is not enough for 1-Gbit DRAM," he said. "Maybe we need 0.11-micron for gigabit. By using 0.11-micron technology, the area would be 208-mm squared, which is not small enough for mass production; however, it could be a product."

Hitoshi Kuyama, senior manager for the DRAM marketing and engineering department at Toshiba's memory division (Yokohama, Japan), agreed that 0.13-micron will not be the optimal process technology for 1-Gbit DRAMs.

"The die size of a 1-Gbit DRAM at 0.13 micron is over 200 millimeters squared," he said. "Usually the biggest die size for a product now is 170-to-180 mm squared. That's the maximum."

What's more, observers said that 1-Gbit DRAMs will be overkill for the memory requirements of low-cost PCs.

Like Fujitsu, Toshiba is also looking to put 512-Mbit DRAMs on its road map. That density is particularly well-suited for Direct Rambus DRAMs because it will provide the right minimum granularity requirements, Toshiba's Kuyama said.

"One CPU, a chip set and one Rambus DRAM can make up one system with 64-Mbytes of memory," he said. "But in the case of SDRAM, it's going to be 256-Mbytes minimum for a x16 size, and that's too big."

Hidemori Inukai, chief manager of memory product development at NEC, said it's becoming more difficult to meet minimum granularity requirements for PCs using traditional power-interface DRAMs, such as SDRAM and EDO DRAMs, because they must accommodate a PC's 64-bit-wide memory path.

To meet the 64-bit bus requirements, a PC requires a minimum of eight 8-bit-wide SDRAMs or four 16-bit-wide SDRAMs on one module, regardless of the density of those chips. If 256-Mbit DRAMs were used to meet those requirements, they produce a minimum granularity of 256 or 128 Mbytes — which exceeds the 64-Mbyte memory requirement assumed for future low-end PCs, observers said.

Another possibility is a 32-bit-wide SDRAM, only two of which would meet the need of a PC's main memory subsystem. But NEC's Inukai said that widening a DRAM's I/O increases its power consumption. "In general we want x-16 from an IC drivability point of view," he said.

Protocol-based Direct Rambus DRAMs, on the other hand, use a special two-byte-wide data path that delivers up to 1.6 Gbytes/second of bandwidth from a single Direct RDRAM. Inukai said the 64-Mbyte minimum granularity that a Rambus DRAM provides in one 512-Mbit chip will likely meet PC makers' target. "By the year 2001, the low end will still probably use 64-Mbytes, so 512-Mbits seems to be a good granularity," he said.

A 0.15-micron process should be adequate to begin mass production of 512-Mbit DRAMs, Toshiba's Kuyama said. At that point, the extra die area needed for Direct Rambus will fall to 10 percent of a chip, he said.

NEC plans to start sampling 512-Mbit DRAMs in the second half of 2000, and should begin production using 0.15-micron design rules by 2001, a company spokesman said.

Based on current memory consumption trends in the PC market, however, it's still unclear whether 1-Gbit DRAMs will be much of a show stopper for volume PC shipments.

"If we don't look at PCs, 1-Gbit is fine for servers or workstations that like to have 10-Gbytes of memory. But from a market size point of view, it's not a huge market," Inukai said. "From the 128-Mbit generation onward, going to twice-bigger densities is fine from both an application and production point of view."



To: unclewest who wrote (24642)7/13/1999 8:04:00 PM
From: Brian1970  Respond to of 93625
 
I'm so glad. I will now share in your glee!!



To: unclewest who wrote (24642)7/14/1999 2:36:00 AM
From: Hunterbob  Read Replies (3) | Respond to of 93625
 
The education-of-the-experts process is getting underway intel.com . This is one of the sessions in "Designing the Next Generation Performance Desktop Systems" at Intel's IDF starting August 31