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To: Clarksterh who wrote (35505)	7/17/1999 6:49:00 PM
From: gdichaz	Respond to of 152472

Clark: Many thanks for your comments. See some more light now through the fog of my earlier (mis)understanding. OTOTOT Since this is the Q board, NSM is just a bit off topic, no? But on the weekend tolerance principle which is time honored on this thread, suggest that anyone here who might be interested, check out George Gilder's National Semi vision. Note he has several "chip" companies in his ascendant technology list and picked NSM early on and continues to suggest that NSM has an approach worth looking at. In brief, while Intel slaughtered NSM which was caught in the flak aimed a AMD, the drive to use NSM's considerable savy and expertise in moving as many functions possible into the smallest space for efficiency reasons attracted his attention. And all within his Telecosm focus. But he speaks best for himself. Just in case anyone misunderstands, no way at all would I compare NSM's future to that of the Q. The Q is the only new gorilla I have found using Mike Buckley's criteria. Know of no others now except the old silverbacks - altho various people on the G&W thread have nominees and candidates, there has been no consensus on any other newbee gorilla yet as best I can tell from following that thread where the "gorilla" experts post. But welcome comments from the articulate G&Wers. Cheers. Chaz

To: Clarksterh who wrote (35505)	7/18/1999 11:14:00 PM
From: quidditch	Read Replies (1) \| Respond to of 152472

Clark, re. ASICs incorporating DSPs and increasing system on chip orientation of Q!(maybe) and NSM, among others. I recall several months ago in one of the thread's analytical cracks at wireless technology that someone, maybe w molloy, engineer (but I don't think so) or someone else saying that running CDMA core and Palm-like computer microprocessor functions (and by extension, 3G multi-media DSP type functions) on the same ASIC would be a significant error, as the added software code required to enable the hard-wired ASIC would leave the chip either error prone or much slower than two separate microprocessors. Any recollection of this? If so, your (or engineer's or w m's )thoughts now.? Regards. Steven