Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: fyo who wrote (66046)	7/19/1999 1:27:00 AM
From: Cirruslvr	Read Replies (1) \| Respond to of 1576281

Fyo - RE: "If we look to the mobile processors for guidance, I believe the following is the benefit of 256kB on-die compared to 512kB half-speed:" Do you have the link to the post I made some time this year when I posted the comparison from Intel's site? Intel changed their benchmarks so you can't compare the two.

To: fyo who wrote (66046)	7/19/1999 10:50:00 AM
From: Process Boy	Read Replies (1) \| Respond to of 1576281

fyo - <Note also the massive increase in SPECfp, which when coupled with a 133MHz FSB and Rambus DRDRAM could well give the CuMine almost exactly the same SPECfp as the Athlon.> I believe you are for the most part addressing a brick wall. The Athlon is a revolutionary chip that has no equal in the universe. Seriously, I believe folks on the thread are trying to compare K63 performance relative to its addition of on-die-cache, and extrapolating that Coppermine will exhibit the same lackluster performance gains. This is a dangerous assumption, IMHO. The P6 core is a different animal from the K6. PB

To: fyo who wrote (66046)	7/19/1999 12:50:00 PM
From: Ali Chen	Read Replies (1) \| Respond to of 1576281

Fyo, <a 133MHz FSB and Rambus DRDRAM could well...SPECfp...> If we want to be in a "dream" mode", how about a 266MHz-SlotA with 2MB cache and 133MHz DDR DRAM (266 MHZ data rate) on the memory side? <the benefit of SSE> I believe there will be no much benefits of SSE (nor 3Dnow) in foreseeable future for SPEC benchmarks. The reason is that the data/instruction flow for efficient SSE application must be hand-crafted. The FORTRAN libraries used in SPEC were polished over years of verification in scientific communities, and they are not going to change overnight. Although there could be some partial effect when using prefetching instructions that are relatively easy to incorporate into generic compilers.

To: fyo who wrote (66046)	7/19/1999 4:38:00 PM
From: Cirruslvr	Read Replies (1) \| Respond to of 1576281

Looks like RamBUST DRDRAM in mass quantities has been DELAYED. "To launch the new Camino 820 chip set, we need a very aggressive Direct Rambus ramp," he said. "It appears that may not happen as quickly as we would like. I expect we will see substantial price premiums." ... "MacWilliams conceded a shift to PC133 could "push out an aggressive Direct RDRAM ramp by a quarter," with the expected shift of mainline desktop PCs to the new memory interface now coming in mid-2000. He added that by then memory makers will have invested sufficiently in back-end assembly and test equipment to mount an aggressive Direct RDRAM production ramp." ebnews.com